TSMC's Advanced Packaging Strategy: CoWoS Outsourcing, EMIB-Like Tech, and 70% Gross Margins

In response, TSMC is scaling its own CoWoS production from approximately 35,000 wafers per month in late 2024 to a target of 120,000–130,000 wafers per month by the end of 2026 — nearly a 4x increase . Bernstein expects total industry CoWoS capacity, including OSAT contributions, to reach about 1.25 million wafers per year .

But the internal scaling alone is not enough. In a major strategic shift, TSMC is now outsourcing not just the simpler WoS (Wafer-on-Substrate) back-end step but also the more complex CoW (Chip-on-Wafer) front-end step to OSAT partners. This outsourcing to ASE, SPIL, and Amkor is expected to begin in the second half of 2026 . Volume estimates for 2026 suggest roughly 240,000–270,000 CoWoS wafers per year will move to OSAT partners — Amkor handling 180,000–190,000, SPIL 60,000–80,000, and ASE tripling its own capacity to 20,000–25,000 wafers per month by end-2026 . ASE has already raised advanced packaging prices 5–20% for 2026 in response to demand .

JPMorgan estimates that from 2026 onward, roughly 70% of back-end steps for CoWoS-L (the highest-end variant used by Nvidia) will be outsourced to ASE and SPIL . The demand is being driven primarily by Nvidia's Rubin architecture and a surge in ASIC designs from hyperscalers .

Developing an "EMIB-Like" Technology to Counter Intel

Intel's EMIB-T (Embedded Multi-die Interconnect Bridge) has gained significant traction. Google reportedly chose it for its 9th-gen TPU, and Intel's CFO claims the foundry is "close to closing some deals that are in the billions per year" on advanced packaging alone . TSMC's CoWoS constraints have pushed some customers to evaluate Intel's alternative .

TSMC's response is an internally developed technology referred to as "EMIB-like" or "quasi-EMIB" . The company is partnering with Taiwan-based IC substrate maker Kinsus to create a bridge-based packaging solution that avoids the large silicon interposers used in CoWoS . Intel's EMIB approach uses small embedded bridge chips only where chiplets need to connect, which lowers material cost and simplifies assembly . TSMC's version is structurally similar .

The project is still in development, but the move signals TSMC's recognition that Intel's EMIB is a "potent contender" and that a complementary or competitive bridge-based offering is needed to prevent customer loss . TrendForce notes that while TSMC retains a lead with its integrated turnkey solution and proven high yields, the growing AI market offers opportunities for both companies . Intel's EMIB-T has reportedly hit 90% yield in technical verification — short of the 98% mass production standard, while TSMC already delivers above 98% on CoWoS packaging for AI accelerators .

Financial and Margin Outlook

TSMC's aggressive packaging strategy is paying off financially. The company reported a gross margin of 66.2% in Q1 2026 and 67.7% in Q2 2026, well above the ~53–54% level a year earlier . Operating margin in Q1 was 58.1% .

For Q2 2026, TSMC guided revenue of $39.0–$40.2 billion and gross margin of 65.5%–67.5% . Actual Q2 revenue came in at $40.2 billion, above the high end . For Q3 2026, TSMC projects revenue of $44.6–$45.8 billion, representing about 12% sequential growth and 37% year-over-year growth at the midpoint .

Analysts expected approximately $40 billion in Q2 2026 revenue (roughly 32% YoY growth) with EPS up over 50% YoY . TrendForce reported that some analysts believed gross margin could approach 70% in Q2 2026 given strong 3nm/5nm AI demand . The Q2 results confirmed that trajectory.

Bernstein raised its TSMC target price citing "more CoWoS, more XPU & 23% revenue growth in 2026," with CoWoS becoming an increasingly meaningful revenue contributor . Advanced packaging contributed approximately 8% of TSMC's total revenue in 2025, with expectations to surpass 10% in 2026 .

The key tension in the strategy is that TSMC's aggressive outsourcing relieves a critical capacity bottleneck but shifts some high-value packaging revenue to OSAT partners. This protects customer relationships and maintains AI chip supply momentum, while the company's core foundry pricing power — especially on 3nm and 5nm nodes — continues to drive overall margins toward 70%.