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AMD MI455X and Helios: Inside the 432GB HBM4 GPU and 72-Chip AI Rack
AMD’s MI455X is an AI accelerator with eight TSMC N2 compute chiplets, N3P fabric/cache and I/O dies, 12 HBM4 stacks, 432GB of memory, 23.3TB/s of bandwidth and up to 40.26 PFLOPS of MXFP4 performance. Helios scales 72 MI455X GPUs across 18 four GPU trays, delivering AMD quoted peaks of 2.9 exaflops of FP4 compute,...
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Key takeaways
- AMD’s MI455X is an AI accelerator with eight TSMC N2 compute chiplets, N3P fabric/cache and I/O dies, 12 HBM4 stacks, 432GB of memory, 23.3TB/s of bandwidth and up to 40.26 PFLOPS of MXFP4 performance.
- Helios scales 72 MI455X GPUs across 18 four GPU trays, delivering AMD quoted peaks of 2.9 exaflops of FP4 compute, 31TB of HBM4 and 1.7PB/s of aggregate memory bandwidth.
- The larger bet is system level: EPYC Venice CPUs, Pensando Vulcano networking, UALink over Ethernet, ROCm and Meta aligned Open Rack Wide standards form one rack scale AI platform rather than a standalone GPU.
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openai.comCreate a landscape editorial hero image for this Studio Global article: What architectural and system-level details did AMD reveal at Hot Chips 2026 about its Instinct MI400 series—especially the MI455X’s TSMC N2. Article summary: AMD’s Hot Chips message was that MI400 is not merely a faster accelerator: it is the compute building block for a vertically integrated, open-standard AI rack. The flagship MI455X combines a large chiplet GPU, unusually . Topic tags: general, general web, user generated, documentation. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, watermarks,
AMD’s Hot Chips 2026 disclosures positioned the Instinct MI400 family as more than a new accelerator generation. The flagship MI455X is the compute tile in Helios, a rack-scale platform that combines GPUs, host CPUs, networking and ROCm software around open infrastructure standards. The key hardware advantage is memory: each MI455X carries 432GB of HBM4, while a 72-GPU Helios rack reaches 31TB of aggregate HBM4 capacity. 2
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MI455X: a chiplet GPU built for AI memory pressure
The MI455X uses AMD’s fifth-generation CDNA architecture. Its compute complex contains eight Accelerator Complex Dies (XCDs) manufactured on TSMC’s N2 process, while fabric/cache and I/O dies use TSMC’s N3P process. AMD combines those chiplets with 12 HBM4 stacks in a TSMC CoWoS-L package. 17
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That partitioning lets AMD use an advanced process where it matters most—the compute dies—while separating fabric, cache and I/O functions into additional chiplets. The package is therefore not simply a larger monolithic GPU; it is a multi-die system designed around bandwidth, yield and rack-scale connectivity.
Core architecture and execution model
AMD lists 256 Work Group Processors (WGPs) and 192MB of global L2 cache for the MI455X. CDNA 5 also introduces matrix-core support for native Wave32 execution, alongside support for the low-precision formats used in modern AI workloads. 3
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The Hot Chips account supplied for this analysis also describes a lower-latency transcendental-function path for operations such as exponentials and logarithms. Those operations occur in parts of neural-network workloads including attention, normalization and activation functions. However, the available sources do not provide a quantified latency reduction, so the feature should not be treated as a measured performance claim.
MI455X specifications at a glance
- Compute architecture: AMD CDNA 5
- Compute chiplets: Eight XCDs on TSMC N2
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- Fabric/cache and I/O: N3P chiplets
- Packaging: TSMC CoWoS-L
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- Work Group Processors: 256
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- Global L2 cache: 192MB
- HBM4: 12 stacks, 432GB total
- Peak memory bandwidth: 23.3TB/s
- Peak OCP MXFP4: 40.26 PFLOPS, listed by AMD as approximately 40.3 PFLOPS
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- Peak MXFP6: 20.13 PFLOPS
- Peak MXFP8: 20.13 PFLOPS
These are peak theoretical figures, not guaranteed application throughput. Actual performance depends on precision, sparsity, model architecture, memory access patterns, software utilization and whether a workload can keep all compute resources occupied.
Why 432GB of HBM4 matters
The MI455X’s most consequential specification may be its memory capacity rather than its headline compute rate. Twelve HBM4 stacks provide 432GB per accelerator and up to 23.3TB/s of bandwidth. 2
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That capacity gives large models more room for weights, activations and inference state—including key-value cache—before data must be distributed across additional accelerators. The benefit is especially relevant for inference, where growing context windows and concurrent requests can make KV-cache capacity a limiting factor.
AMD supports a broad set of CDNA 5 data types, including OCP MXFP4, MXFP6, MXFP8, OCP FP8, BF16, FP16, TF32, FP32 and FP64. The low-precision formats are aimed at efficient AI training and inference, while the broader format support keeps the architecture relevant to HPC and mixed workloads. 18
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Helios turns MI455X into a rack-scale system
Helios organizes the accelerators into 18 Open Rack Wide-aligned compute trays, with four MI455X GPUs per tray for a total of 72 GPUs. AMD quotes the following rack-level maximums:
- 2.9 exaflops of FP4 compute
- 1.4 exaflops of FP8 compute
- 31TB of aggregate HBM4 capacity
- 1.7PB/s of aggregate HBM bandwidth
- 260TB/s of scale-up bandwidth
- 43TB/s of scale-out bandwidth
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The rack’s value is not just the multiplication of 72 GPU specifications. Helios is designed as one scale-up domain, so communication between accelerators becomes a central part of the architecture rather than an afterthought handled by separate servers. AMD’s published design uses UALink over Ethernet for scale-up connectivity and Ethernet-based networking for scale-out. 10
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CPUs, trays and networking
Each four-GPU tray is paired with an AMD EPYC “Venice” host processor. Reporting on the Hot Chips system architecture identifies the host platform as EPYC 9006 on SP7, while AMD describes Helios as combining sixth-generation EPYC 9006-series CPUs with MI455X GPUs and Pensando networking. 7
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Pensando Vulcano AI NICs provide 800Gbps Ethernet connectivity for scale-out traffic. AMD’s Helios materials specify up to 2.4Tbps of scale-out bandwidth per GPU for the Vulcano-based design. 47
This division of labor is important: the GPU handles matrix and vector computation, the EPYC processor handles host and control-plane tasks, and the network fabric moves data within and beyond the rack. Helios is consequently a co-designed compute system, not a collection of identical accelerator cards.
The Open Rack Wide and ROCm strategy
AMD is aligning Helios with Meta’s Open Rack Wide approach and broader Open Compute Project rack standards. The company is also using UALink and Ethernet-based fabrics instead of presenting the rack as a proprietary closed system. 47
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The standards-based approach supports AMD’s broader argument that customers should be able to assemble large AI systems from interoperable components. In AMD’s positioning, the stack includes:
- Instinct MI455X: matrix and vector acceleration
- EPYC Venice: host and control-plane compute
- Pensando Vulcano: scale-out networking
- UALink over Ethernet: scale-up connectivity
- ROCm: the software environment intended to provide an alternative to CUDA-dependent infrastructure
ROCm does not by itself eliminate the engineering work involved in moving software between GPU platforms. Kernel support, libraries, compilers, model frameworks and production tooling still determine how easily a workload transfers. The strategic point is that AMD is attempting to offer the complete hardware and software foundation needed to deploy a large AI cluster, rather than competing only on accelerator specifications.
Deployment timing: a target, not proof of broad availability
AMD has said that Helios is entering production, with deployments beginning in the second half of 2026. 4
49 That statement describes AMD’s production and deployment timetable; it should not be read as evidence that the platform is already broadly installed or that every quoted rack configuration is available at volume.
Microsoft has separately announced plans to deploy Helios on Azure for frontier-model inference, providing a named cloud deployment path for the platform. 54
56 As with AMD’s performance figures, customer deployment plans are not the same as independently measured production results.
Versal Premium Gen 2 extends the strategy beyond data-center GPUs
AMD’s Hot Chips presence also covered Versal Premium Gen 2 adaptive SoCs, which address a different part of the compute market. These devices target data-intensive and latency-sensitive applications such as physical AI, networking, test and measurement, professional video, aerospace and defense, and other mission-critical systems. 31
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The Memory-on-Package versions integrate up to 32GB of LPDDR5X directly into the package. AMD specifies up to 288GB/s of projected bandwidth and claims up to a 60% reduction in board area compared with designs using external memory. 36
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For the broader Versal Premium Gen 2 family, AMD’s official specifications list hardened PCIe Gen6 and CXL 3.1 interfaces, along with LPDDR5X and DDR5 memory support. 37
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Some Hot Chips reporting discusses PCIe Gen7-capable transceivers and post-quantum cryptography in the context of the platform’s broader capabilities. The authoritative product material supplied here confirms PCIe Gen6, CXL 3.1 and security features such as PCIe Integrity and Data Encryption, but does not establish PCIe Gen7 or hardened post-quantum cryptography as confirmed specifications for every Memory-on-Package device. 37
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The main takeaway
MI455X’s headline numbers—432GB of HBM4, 23.3TB/s of bandwidth and 40.26 PFLOPS of MXFP4—matter because they support AMD’s larger system design. Helios places 72 of these accelerators into a rack with 31TB of HBM4, exaflop-class low-precision compute, high-bandwidth scale-up links, EPYC host CPUs and Pensando networking.
AMD’s competitive bet is therefore architectural as much as numerical: make the GPU, memory, fabric, host processor, NIC, rack and software stack work as one open-standards platform. Whether that translates into competitive production performance will depend on real workloads, software maturity, supply and deployment scale—not peak specifications alone.
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What is the short answer to "AMD MI455X and Helios: Inside the 432GB HBM4 GPU and 72-Chip AI Rack"?
AMD’s MI455X is an AI accelerator with eight TSMC N2 compute chiplets, N3P fabric/cache and I/O dies, 12 HBM4 stacks, 432GB of memory, 23.3TB/s of bandwidth and up to 40.26 PFLOPS of MXFP4 performance.
What are the key points to validate first?
AMD’s MI455X is an AI accelerator with eight TSMC N2 compute chiplets, N3P fabric/cache and I/O dies, 12 HBM4 stacks, 432GB of memory, 23.3TB/s of bandwidth and up to 40.26 PFLOPS of MXFP4 performance. Helios scales 72 MI455X GPUs across 18 four GPU trays, delivering AMD quoted peaks of 2.9 exaflops of FP4 compute, 31TB of HBM4 and 1.7PB/s of aggregate memory bandwidth.
What should I do next in practice?
The larger bet is system level: EPYC Venice CPUs, Pensando Vulcano networking, UALink over Ethernet, ROCm and Meta aligned Open Rack Wide standards form one rack scale AI platform rather than a standalone GPU.