TSMC's 50x Silicon Photonics Bet: How COUPE Will Reshape AI Data Centers by 2028

The Capacity Targets: 500 to 25,000 Wafers Per Month

The expansion plan is sharply tiered. According to recent reports from Commercial Times and TrendForce, TSMC's PIC capacity will climb from roughly 500 wafers per month today to 10,000 wafers per month by the second quarter of 2026. By the fourth quarter of 2026, that number rises to 15,000, and the target for 2028 is at least 25,000 wafers per month ^MTT.

At an estimated 648 die per wafer, the 2028 run-rate would yield roughly 194 million PIC die annually at full output ^T1. For context, the current capacity of ~500 wafers per month yields about 4 million die per year ^T.

Key Customers: NVIDIA and Broadcom Lead the Charge

NVIDIA and Broadcom are identified as the early lead customers for COUPE volume production, with reports indicating orders have already been placed ^MAE. Given limited PIC production capacity during the initial ramp in 2026–2027, these two companies are expected to be the primary beneficiaries of early output ^T.

NVIDIA has moved aggressively to secure its optical supply chain. In March 2026, the company invested $4 billion ($2 billion each) in Lumentum and Coherent, locking in multi-year procurement commitments for high-performance laser chips and advanced optical materials ^EL. NVIDIA plans to deploy COUPE-based switches, including Spectrum-X Ethernet photonics switches in the second half of 2026, using TSMC's SoIC technology ^R.

The Technology: COUPE + SoIC-X

COUPE is fundamentally a packaging innovation. It uses TSMC's advanced SoIC-X (System on Integrated Chips) technology to stack an electronic integrated circuit (EIC) directly on top of a photonic integrated circuit (PIC) using hybrid copper-to-copper bonding ^STS. The EIC is produced at a 65nm-class process node, while the PIC handles the optical signaling ^SS.

This heterogeneous integration is the key enabler. By bonding the electronic and photonic dies at sub-ten-micrometer pitch, TSMC claims COUPE delivers 5–10x improvement in power efficiency, 10–20x lower latency, and a more compact footprint compared to traditional pluggable optical modules ^T.

The approach has attracted a broader ecosystem. TSMC has partnered with EDA tool vendors Ansys, Synopsys, and Cadence to support photonic design, and Himax has been confirmed as the exclusive supplier of micro-lens arrays for the first two COUPE generations ^SLM.

The CPO Market Reaches an Inflection Point in 2026

2026 is widely described as the year co-packaged optics (CPO) transitions from pilot deployments to full-scale commercial production ^HG. Multiple market research reports converge on this timeline: the CPO market is estimated at $2.2–$4.2 billion in 2026, with a projected compound annual growth rate of 25–35% through 2031 ^G. IDTechEx projects the market will exceed $20 billion by 2036, growing at a 37% CAGR ^I.

AI data centers are the primary demand driver. NVIDIA's Spectrum-6 Ethernet switch, unveiled at CES 2026, delivers 409.6 Tbps aggregate bandwidth using integrated silicon photonic engines and reduces interconnect power consumption by 5x compared to the previous generation ^M. Broadcom and Marvell are also developing CPO platforms targeting 1.6T and beyond ^AP.

The power-efficiency story is compelling. Traditional copper and pluggable systems consumed 12–15 picojoules per bit in early 2025, while new CPO systems from Broadcom and NVIDIA operate at 5 pJ/bit or lower, with a roadmap toward under 1 pJ/bit ^MF.

Yield Challenges and Packaging Constraints

The expansion plan carries significant risk. Reports cite a hypothetical SoIC stacking yield of roughly 50% for early production, which would effectively halve the number of finished optical engines relative to raw PIC die counts ^T1. When downstream assembly yield losses are factored in, actual optical engine shipments could be substantially lower—an estimated 39 million units at current capacity rising to 486 million at the 2028 target, versus the 194 million raw die count ¹.

Advanced packaging capacity is itself a bottleneck. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) capacity has been sold out through 2026, and CEO C.C. Wei has publicly acknowledged that CoWoS remains extremely tight ^O. TSMC projects CoWoS capacity growing at more than 80% CAGR from 2022 to 2027, but silicon photonics is now competing for the same advanced-packaging complex—CoWoS and SoIC—that GPU and HBM integration already strains ^TB. Industry analysts describe TSMC's silicon photonics capacity as the next likely AI supply-chain bottleneck after CoWoS ^MB.

Summary: TSMC's PIC Capacity Roadmap

The Bottom Line

TSMC is executing a historically aggressive capacity expansion in silicon photonics, anchored by the COUPE/SoIC-X platform and fueled by AI data-center demand. The ramp from 500 to 25,000 wafers per month in under three years represents a 50x increase, with implications for the entire AI hardware supply chain. However, yield maturity—particularly SoIC stacking yields in the ~50% range—and the broader advanced-packaging bottleneck remain the biggest near-term risks ^MHTM.

If successful, TSMC's bet on light will cement its role as the central foundry for AI-era interconnect technology, extending its dominance beyond logic and advanced packaging into the optical domain.