Intel's 1.4nm (14A2) Chip Process: Dual-Side Power Delivery, Roadmap Milestones, and How It Stacks Up Against TSMC

This dual-side architecture is intended to enable tighter metal pitches and higher transistor density than the base 14A implementation ^M. Specifically:

• Base 14A M0 metal pitch: 28nm ^M.
• 14A2 target M0 metal pitch: ~21nm, enabled by double-patterning enhancements made possible by the dual-side power approach ^M.

Because base 14A already promises up to ~30% chip density improvement over Intel 18A, the 14A2 variant could offer a larger density gain — though Intel has not published an exact figure for 14A2 in available sources ^ME.

What's Driving This Change

The shift is framed as a direct response to competitive pressure from TSMC's A14 (1.4nm-class) and Samsung's SF1.4 efforts ^M. As the 1.4nm race tightens, Intel needs a density differentiator beyond what the base 14A node offers. Dual-side power delivery is reportedly a way to achieve that, though it introduces technical challenges including increased electrical resistance and the need for new composite power-delivery structures ^M.

Key Roadmap Milestones (Intel 14A / 14A2)

Intel CEO Lip-Bu Tan has provided updated timeline guidance. The following table summarizes the key milestones based on recent reports and Intel's own disclosures:

Tan has referred to the 0.9 PDK as the "Holy Grail" of the 14A process, noting that it is a critical checkpoint for customer engagement ^W. The schedule represents roughly a one-year slip from earlier guidance that targeted 2027 risk production ^S.

Timeline Comparison vs. TSMC and Samsung

TSMC plans to begin production of its A14 fabrication process in 2028, according to a Bloomberg report ^B. Multiple other sources corroborate a 2028 HVM target for TSMC's A14 ^BT. Notably, the first version of TSMC's A14 will not include backside power delivery; a variant with backside power rails (A14P) is planned for 2029 ^T.

Samsung is referenced as part of the broader 1.4nm competitive landscape, but the provided sources do not establish a current confirmed risk-production or mass-production schedule for SF1.4 ^M.

Key takeaway: Intel's reported 2029 volume-production target trails TSMC's reported 2028 A14 production timing by roughly one year. However, Tan has stated that Intel sees 14A timing as lining up closely with TSMC's A14, with both positioned in the 1.4nm class ^W. Samsung's timeline remains less certain ^M.

Broader Ambitions Beyond 14A

CEO Lip-Bu Tan has reportedly confirmed that Intel has already kicked off development on two process nodes beyond 14A ^G:

• 10A (1nm-class) — now in early development ^G.
• 7A (sub-1nm) — also in early development ^G.

Tan revealed this while discussing Intel's process roadmap at J.P. Morgan's 54th annual Global Technology, Media and Communications Conference in Boston ^G. This indicates Intel is mapping out a multi-generational angstrom-era roadmap well beyond 14A.

Summary

Intel's base 14A node uses RibbonFET 2 gate-all-around transistors and PowerDirect backside power delivery, delivering up to 30% chip-density improvement over Intel 18A ^E. The reported 14A2 variant is being considered with a dual-side power delivery architecture and a tighter 21nm M0 pitch to compete on density ^M. Key milestones are PDK 0.9 in October 2026, risk production in 2028, and HVM in 2029 ^EGBWS. That timeline puts Intel about one year behind TSMC's reported A14 production target of 2028 ^BB. Beyond 14A, Intel is developing 10A and 7A process nodes for the longer term ^G.