Production data from the Tau Scaling Law paper

Huawei disclosed that over the past six years it has designed and mass-produced 381 chips based on the Tau Scaling Law, serving smartphones, AI accelerators, automotive electronics, and infrastructure . The key figures reported for the Kirin 2026 include:

• Transistor density: 238 million transistors per square millimeter (MTr/mm²), a 53.5–55% increase from the previous generation's 155 MTr/mm² on the same process node .
• Energy efficiency gain: 40–41% improvement in performance-core power efficiency .
• Peak clock frequency: Approximately 3.1 GHz for the performance cores .
• Roadmap target: By 2031, Huawei expects high-end chips based on the Tau Scaling Law to reach a transistor density equivalent to a 1.4 nm (14 Å) process node .

How LogicFolding improves signal propagation at a 1.5 µm bonding pitch

LogicFolding is a 3D chip architecture that "folds" logic circuits from a single planar layer into two or more vertically stacked active layers . The primary mechanism works through two interconnected innovations:

• Shortened critical-path wiring: By distributing critical logic paths across stacked layers, the physical distance signals must travel is drastically reduced, cutting resistive-capacitive (RC) delay, which is the dominant component of signal propagation time .
• Ultra-fine 1.5 µm hybrid bonding pitch: Huawei's 2026 Kirin uses a 1.5 µm bond-pitch 3D-stacked architecture enabled by advanced wafer-to-wafer hybrid bonding . This provides compared to typical through-silicon vias (TSVs), allowing fine-grained architectural splitting across dies and further optimizing routing .

The combined effect directly compresses the time constant τ (signal propagation delay)—the central optimization target of the Tau Scaling Law—rather than relying on smaller transistor geometries . He Tingbo stated that while previous generations took three years to move density from 126 to 155 MTr/mm², LogicFolding achieved the jump to 238 MTr/mm² in a single generation .

Transistor density without a smaller process node

Huawei achieved 238 million transistors per square millimeter (MTr/mm²) on the Kirin 2026 chip without moving to a smaller manufacturing node . The density is comparable to TSMC's 3 nm process and Intel's 18A node, achieved on existing Chinese fabrication infrastructure that is widely assumed to be SMIC's 7nm-class DUV-based processes .

How this strategy helps Huawei bypass U.S. EUV export controls

U.S. export controls prevent Huawei from purchasing ASML's EUV (extreme ultraviolet) lithography machines, which are required to pattern the smallest transistor features below 7 nm. Huawei's strategy circumvents this constraint through several interconnected tactics:

• Shifting the metric: The Tau Scaling Law replaces geometric scaling (Moore's Law) with time scaling, optimizing signal propagation delay (τ) through architectural and 3D innovation rather than lithographic shrink .
• Lithography-agnostic density gains: LogicFolding's density increase comes from vertical stacking and shorter interconnects, not from finer photolithography. This allows Huawei to extract more performance from existing sanction-compatible process nodes .
• Hybrid bonding as an EUV substitute: Huawei's aggressive 1.5 µm hybrid bonding pitch delivers dense vertical interconnects without requiring EUV equipment. Analyst firm SemiAnalysis noted that this appears to leapfrog competitors in advanced hybrid bonding technology .
• 2031 roadmap to 1.4 nm equivalent: By refining LogicFolding-style 3D integration, Huawei claims it can reach transistor density equivalent to a 1.4 nm process by 2031 without ever accessing EUV tools .

NVIDIA CEO Jensen Huang commented that the Tau Scaling Law represents "a breakthrough" but added that it poses "no threat to TSMC" .

Important caveat: No independent verification

Huawei has not published independent benchmark data or disclosed which specific Chinese foundry (widely assumed to be SMIC) manufactures the Kirin 2026 . Several analysts and publications, including The Register and Tech Times, have noted that the claims should be treated with caution until third-party testing confirms the performance . Until such verification appears, the reported figures remain Huawei's own characterization.

Production data from the Tau Scaling Law paper

Huawei disclosed that over the past six years it has designed and mass-produced 381 chips based on the Tau Scaling Law, serving smartphones, AI accelerators, automotive electronics, and infrastructure . The key figures reported for the Kirin 2026 include:

• Transistor density: 238 million transistors per square millimeter (MTr/mm²), a 53.5–55% increase from the previous generation's 155 MTr/mm² on the same process node .
• Energy efficiency gain: 40–41% improvement in performance-core power efficiency .
• Peak clock frequency: Approximately 3.1 GHz for the performance cores .
• Roadmap target: By 2031, Huawei expects high-end chips based on the Tau Scaling Law to reach a transistor density equivalent to a 1.4 nm (14 Å) process node .

How LogicFolding improves signal propagation at a 1.5 µm bonding pitch

LogicFolding is a 3D chip architecture that "folds" logic circuits from a single planar layer into two or more vertically stacked active layers . The primary mechanism works through two interconnected innovations:

• Shortened critical-path wiring: By distributing critical logic paths across stacked layers, the physical distance signals must travel is drastically reduced, cutting resistive-capacitive (RC) delay, which is the dominant component of signal propagation time .
• Ultra-fine 1.5 µm hybrid bonding pitch: Huawei's 2026 Kirin uses a 1.5 µm bond-pitch 3D-stacked architecture enabled by advanced wafer-to-wafer hybrid bonding . This provides compared to typical through-silicon vias (TSVs), allowing fine-grained architectural splitting across dies and further optimizing routing .

The combined effect directly compresses the time constant τ (signal propagation delay)—the central optimization target of the Tau Scaling Law—rather than relying on smaller transistor geometries . He Tingbo stated that while previous generations took three years to move density from 126 to 155 MTr/mm², LogicFolding achieved the jump to 238 MTr/mm² in a single generation .

Transistor density without a smaller process node

Huawei achieved 238 million transistors per square millimeter (MTr/mm²) on the Kirin 2026 chip without moving to a smaller manufacturing node . The density is comparable to TSMC's 3 nm process and Intel's 18A node, achieved on existing Chinese fabrication infrastructure that is widely assumed to be SMIC's 7nm-class DUV-based processes .

How this strategy helps Huawei bypass U.S. EUV export controls

U.S. export controls prevent Huawei from purchasing ASML's EUV (extreme ultraviolet) lithography machines, which are required to pattern the smallest transistor features below 7 nm. Huawei's strategy circumvents this constraint through several interconnected tactics:

• Shifting the metric: The Tau Scaling Law replaces geometric scaling (Moore's Law) with time scaling, optimizing signal propagation delay (τ) through architectural and 3D innovation rather than lithographic shrink .
• Lithography-agnostic density gains: LogicFolding's density increase comes from vertical stacking and shorter interconnects, not from finer photolithography. This allows Huawei to extract more performance from existing sanction-compatible process nodes .
• Hybrid bonding as an EUV substitute: Huawei's aggressive 1.5 µm hybrid bonding pitch delivers dense vertical interconnects without requiring EUV equipment. Analyst firm SemiAnalysis noted that this appears to leapfrog competitors in advanced hybrid bonding technology .
• 2031 roadmap to 1.4 nm equivalent: By refining LogicFolding-style 3D integration, Huawei claims it can reach transistor density equivalent to a 1.4 nm process by 2031 without ever accessing EUV tools .

NVIDIA CEO Jensen Huang commented that the Tau Scaling Law represents "a breakthrough" but added that it poses "no threat to TSMC" .

Important caveat: No independent verification

Huawei has not published independent benchmark data or disclosed which specific Chinese foundry (widely assumed to be SMIC) manufactures the Kirin 2026 . Several analysts and publications, including The Register and Tech Times, have noted that the claims should be treated with caution until third-party testing confirms the performance . Until such verification appears, the reported figures remain Huawei's own characterization.