bLLC stands for Big Last-Level Cache. Leaks consistently describe it as Intel's direct response to AMD's 3D V-Cache / X3D technology, aiming to provide a significant L3 cache boost for gaming and memory-sensitive workloads . The cache is not a single size across the lineup; it is segmented by SKU tier :

• Core Ultra 9 (Flagship): Up to 288 MB of bLLC, achieved via a dual-tile design (2 × 144 MB dies) .
• Core Ultra 7: Up to 144 MB of bLLC, likely on a single compute tile .
• Lower-tier Core Ultra 5 and Core Ultra 3 bLLC details are less clearly supported by the available leaks, though some reports suggest bLLC may appear in locked-multiplier (non-K) SKUs as well .

The placement of the bLLC on the ringbus within each compute tile is also a notable architectural detail . Intel's performance claims against AMD's X3D lineup remain unverified by independent benchmarks .

Core Configurations and Power Variants

Flagship — 52-Core Dual-Tile Design

The highest-end Nova Lake-S SKU is reported to feature a dual-compute-tile design with a total of 52 cores and 52 threads (hyperthreading is reportedly dropped for this generation) . Leaks agree on this configuration :

• 16x "Coyote Cove" Performance cores (P-cores)
• 32x "Arctic Wolf" Efficiency cores (E-cores)
• 4x low-power E-cores (LP-E)
• Total: 52 cores, 52 threads

A previously rumored 42-core variant was later reported to have been upgraded to 44 cores . The newer configuration is described as 16 P-cores, 24 E-cores, and 4 LP-E cores . This change is believed to free up a fully enabled compute tile that could trickle down into other SKUs .

Mid-Range — Single-Tile Designs

Below the flagship, single-compute-tile SKUs are expected. A prominent rumored configuration is a 28-core part, which is often reported as 8 P-cores + 16 E-cores + 4 LP-E cores . These parts are expected to carry the Core Ultra 7 branding and feature 144 MB of bLLC . Another configuration, likely a 24-core part (4P+16E+4LPE), has also been mentioned .

Entry-Level

Details for entry-level Core Ultra 5 and Core Ultra 3 models are less concrete, but leaks suggest configurations such as 8P+16E+4LPE, 8P+12E+4LPE, 6P+8E+4LPE, 4P+8E+4LPE, and 4P+4E+4LPE . Most of these are expected to be single-tile, non-bLLC parts . Power consumption for these lower-tier SKUs is rumored to be under 125W .

Power and Thermal Headroom

Leaks indicate that power and thermal management is a major engineering focus for the 52-core flagship . At Computex 2026, industry chatter suggested the chip would feature multi-core overclocking capabilities, requiring significant thermal headroom . Specific TDPs remain unconfirmed by Intel .

Broader Nova Lake-S Desktop Lineup

The Nova Lake-S family is expected to span from entry-level to flagship, segmented by compute tile count, bLLC cache size, and core count :

The compute silicon for the flagship is reported to be manufactured on TSMC's N2P process node .

Platform: Socket, Chipset, and Memory

LGA 1954 Socket

All reliable leaks point to a new LGA 1954 socket for Nova Lake-S, replacing the LGA 1851 socket used by Arrow Lake-S . This means existing motherboards will not be compatible .

900-Series Chipsets

The platform is expected to launch with Intel's 900-series chipsets . Enthusiast-tier chatter specifically mentions Z990 and Z970 boards, alongside a mainstream B960 chipset .

Memory Support — DDR5-8000

Nova Lake-S is expected to natively support DDR5-8000 memory . This represents a 25% increase over Arrow Lake-S's native DDR5-6400 support . Memory modules may utilize CUDIMM and CQDIMM standards to achieve these higher frequencies .

Launch Timeline: A Shift to CES 2027

The launch window for Nova Lake-S has been a moving target, shifting from late 2026 to early 2027, based on multiple leak reports :

• Early Leaks (2025): Targeted a late 2026 or broad 2026 launch window .
• February 2026 Leak: A delay toward CES 2027 was reported by a prominent leaker .
• Computex 2026 Chatter (June 2026): Industry sources suggested a Q1 2027 launch, with the official announcement expected during CES 2027 and retail availability several weeks later . Some reports suggest the 52-core flagship may arrive 2-3 months after the initial 28-core launch, possibly around Computex 2027 .

Current reading: The most consistent leak-based consensus points to a Q1 2027 launch event at CES 2027, with retail availability to follow . Intel has not officially confirmed any dates .

Important Caveats

• Nothing is officially confirmed by Intel. The first concrete socket, motherboard, and chipset details remain at leak level .
• Launch timelines have shifted multiple times and may continue to change .
• bLLC performance versus AMD's 3D V-Cache is entirely unproven until independent benchmarks are available .
• Some leaks disagree on specific core counts and SKU names, so treat exact lineup details as speculative .

bLLC stands for Big Last-Level Cache. Leaks consistently describe it as Intel's direct response to AMD's 3D V-Cache / X3D technology, aiming to provide a significant L3 cache boost for gaming and memory-sensitive workloads . The cache is not a single size across the lineup; it is segmented by SKU tier :

• Core Ultra 9 (Flagship): Up to 288 MB of bLLC, achieved via a dual-tile design (2 × 144 MB dies) .
• Core Ultra 7: Up to 144 MB of bLLC, likely on a single compute tile .
• Lower-tier Core Ultra 5 and Core Ultra 3 bLLC details are less clearly supported by the available leaks, though some reports suggest bLLC may appear in locked-multiplier (non-K) SKUs as well .

The placement of the bLLC on the ringbus within each compute tile is also a notable architectural detail . Intel's performance claims against AMD's X3D lineup remain unverified by independent benchmarks .

Core Configurations and Power Variants

Flagship — 52-Core Dual-Tile Design

The highest-end Nova Lake-S SKU is reported to feature a dual-compute-tile design with a total of 52 cores and 52 threads (hyperthreading is reportedly dropped for this generation) . Leaks agree on this configuration :

• 16x "Coyote Cove" Performance cores (P-cores)
• 32x "Arctic Wolf" Efficiency cores (E-cores)
• 4x low-power E-cores (LP-E)
• Total: 52 cores, 52 threads

A previously rumored 42-core variant was later reported to have been upgraded to 44 cores . The newer configuration is described as 16 P-cores, 24 E-cores, and 4 LP-E cores . This change is believed to free up a fully enabled compute tile that could trickle down into other SKUs .

Mid-Range — Single-Tile Designs

Below the flagship, single-compute-tile SKUs are expected. A prominent rumored configuration is a 28-core part, which is often reported as 8 P-cores + 16 E-cores + 4 LP-E cores . These parts are expected to carry the Core Ultra 7 branding and feature 144 MB of bLLC . Another configuration, likely a 24-core part (4P+16E+4LPE), has also been mentioned .

Entry-Level

Details for entry-level Core Ultra 5 and Core Ultra 3 models are less concrete, but leaks suggest configurations such as 8P+16E+4LPE, 8P+12E+4LPE, 6P+8E+4LPE, 4P+8E+4LPE, and 4P+4E+4LPE . Most of these are expected to be single-tile, non-bLLC parts . Power consumption for these lower-tier SKUs is rumored to be under 125W .

Power and Thermal Headroom

Leaks indicate that power and thermal management is a major engineering focus for the 52-core flagship . At Computex 2026, industry chatter suggested the chip would feature multi-core overclocking capabilities, requiring significant thermal headroom . Specific TDPs remain unconfirmed by Intel .

Broader Nova Lake-S Desktop Lineup

The Nova Lake-S family is expected to span from entry-level to flagship, segmented by compute tile count, bLLC cache size, and core count :

The compute silicon for the flagship is reported to be manufactured on TSMC's N2P process node .

Platform: Socket, Chipset, and Memory

LGA 1954 Socket

All reliable leaks point to a new LGA 1954 socket for Nova Lake-S, replacing the LGA 1851 socket used by Arrow Lake-S . This means existing motherboards will not be compatible .

900-Series Chipsets

The platform is expected to launch with Intel's 900-series chipsets . Enthusiast-tier chatter specifically mentions Z990 and Z970 boards, alongside a mainstream B960 chipset .

Memory Support — DDR5-8000

Nova Lake-S is expected to natively support DDR5-8000 memory . This represents a 25% increase over Arrow Lake-S's native DDR5-6400 support . Memory modules may utilize CUDIMM and CQDIMM standards to achieve these higher frequencies .

Launch Timeline: A Shift to CES 2027

The launch window for Nova Lake-S has been a moving target, shifting from late 2026 to early 2027, based on multiple leak reports :

• Early Leaks (2025): Targeted a late 2026 or broad 2026 launch window .
• February 2026 Leak: A delay toward CES 2027 was reported by a prominent leaker .
• Computex 2026 Chatter (June 2026): Industry sources suggested a Q1 2027 launch, with the official announcement expected during CES 2027 and retail availability several weeks later . Some reports suggest the 52-core flagship may arrive 2-3 months after the initial 28-core launch, possibly around Computex 2027 .

Current reading: The most consistent leak-based consensus points to a Q1 2027 launch event at CES 2027, with retail availability to follow . Intel has not officially confirmed any dates .

Important Caveats

• Nothing is officially confirmed by Intel. The first concrete socket, motherboard, and chipset details remain at leak level .
• Launch timelines have shifted multiple times and may continue to change .
• bLLC performance versus AMD's 3D V-Cache is entirely unproven until independent benchmarks are available .
• Some leaks disagree on specific core counts and SKU names, so treat exact lineup details as speculative .