For Humufish specifically, Google's compute die will be manufactured in-house, while MediaTek handles the back-end design. The chip is expected in the second half of 2027 . Aletheia Capital estimates the Humufish die area at 9–10x reticle size with a substrate of roughly 13,700 mm² (16x reticle), making it too large and expensive for CoWoS — EMIB-T is the default packaging, with CoPoS as a backup .

In short, Google needed a packaging solution that could scale to mega-packages that CoWoS would struggle with economically. EMIB-T is the answer.

Technical Advantages: How EMIB-T Differs from CoWoS

The architectural difference between EMIB-T and CoWoS is fundamental. CoWoS mounts every die on a large silicon interposer that spans the entire package — a costly slab that wastes silicon at the edges as package sizes grow . EMIB, by contrast, embeds small silicon bridges into the organic substrate only where dies connect, leaving the rest of the substrate as cheap organic material .

The difference is often described as a city-wide highway network (CoWoS) vs. a bridge at a river crossing (EMIB) . For Humufish's ~10x reticle die, that cost and scaling advantage is decisive.

The 90% Yield Cliff: A Problem Harder Than It Sounds

Google has placed an order for Intel to build more than 3 million TPUs in 2028, confirmed by The Information citing four sources . Industry analysis suggests this is primarily an advanced packaging engagement, as Intel's own process nodes are not competitive with TSMC for leading-edge logic .

But the volume target runs headlong into a manufacturing reality: Intel's EMIB-T has achieved roughly 90% technology-validation yield for the Humufish project . Analyst Ming-Chi Kuo says this is a positive signal given Intel's EMIB production history, but the benchmark is FCBGA assembly yield, which the industry runs at 98%+ . Kuo explicitly warns that climbing from 90% to 98% may be "more difficult than getting from 0% to 90%" .

TSMC, for reference, targets 98% production yield for its 5.5-reticle CoWoS in 2026 — a significantly higher baseline . This yield gap means Intel must solve an extremely hard manufacturing-ramp problem to make the 3-million-unit volume economically viable. Every percentage point of yield loss on a high-value AI accelerator costing hundreds or thousands of dollars translates directly into tens of millions in lost revenue.

Intel is ramping its Project Pelican advanced packaging complex in Malaysia, slated to become operational in 2026 . Even so, hitting multi-million-unit output at high yield for a single customer in a new technology variant (EMIB-T) would be unprecedented for Intel's foundry packaging business.

The Ironic Contradiction: Intel Drops EMIB for Its Own Flagship CPU

Perhaps the most awkward element of Google's EMIB-T bet is this: Intel's own upcoming Diamond Rapids Xeon processor will not use EMIB. According to SemiAnalysis (via LinkedIn), "Intel Abandons EMIB for UCIe in Diamond Rapids… Diamond Rapids will likely use UCIe over substrate for a long-reach die-to-die interconnect instead" . Intel showed a UCIe-based die-to-die link at ISSCC .

This creates a sharp irony: Intel is selling EMIB-T to Google as its marquee external packaging customer while abandoning it internally for its own flagship server CPU. The rationale is that for monolithic-ish CPU chiplets, UCIe over standard substrate offers sufficient bandwidth with lower cost and complexity — but the optics are awkward.

Intel is effectively asking the market to trust EMIB for Google's 3-million-unit TPU volume, yet its own premier product team chose a different interconnect standard. As SemiAnalysis put it, "Intel's 'best' packaging tech — for everyone but Intel" .

Note: The Diamond Rapids design details are drawn from industry analyst reports and LinkedIn posts from SemiAnalysis, which are credible but not official Intel confirmations .

Bottom Line

Google's EMIB-T bet is a vote of confidence in Intel's packaging at a moment when CoWoS capacity is strangled, and for very large die sizes (~10x reticle) EMIB-T offers genuine cost and scaling advantages. But Intel faces a steep yield climb (90% → 98%+) and a multi-million-unit volume ramp with a technology it has never run at that scale. The contradiction that Diamond Rapids drops EMIB underscores how Intel promotes the technology for external customers while migrating its own highest-volume product to a different standard.

For Humufish specifically, Google's compute die will be manufactured in-house, while MediaTek handles the back-end design. The chip is expected in the second half of 2027 . Aletheia Capital estimates the Humufish die area at 9–10x reticle size with a substrate of roughly 13,700 mm² (16x reticle), making it too large and expensive for CoWoS — EMIB-T is the default packaging, with CoPoS as a backup .

In short, Google needed a packaging solution that could scale to mega-packages that CoWoS would struggle with economically. EMIB-T is the answer.

Technical Advantages: How EMIB-T Differs from CoWoS

The architectural difference between EMIB-T and CoWoS is fundamental. CoWoS mounts every die on a large silicon interposer that spans the entire package — a costly slab that wastes silicon at the edges as package sizes grow . EMIB, by contrast, embeds small silicon bridges into the organic substrate only where dies connect, leaving the rest of the substrate as cheap organic material .

The difference is often described as a city-wide highway network (CoWoS) vs. a bridge at a river crossing (EMIB) . For Humufish's ~10x reticle die, that cost and scaling advantage is decisive.

The 90% Yield Cliff: A Problem Harder Than It Sounds

Google has placed an order for Intel to build more than 3 million TPUs in 2028, confirmed by The Information citing four sources . Industry analysis suggests this is primarily an advanced packaging engagement, as Intel's own process nodes are not competitive with TSMC for leading-edge logic .

But the volume target runs headlong into a manufacturing reality: Intel's EMIB-T has achieved roughly 90% technology-validation yield for the Humufish project . Analyst Ming-Chi Kuo says this is a positive signal given Intel's EMIB production history, but the benchmark is FCBGA assembly yield, which the industry runs at 98%+ . Kuo explicitly warns that climbing from 90% to 98% may be "more difficult than getting from 0% to 90%" .

TSMC, for reference, targets 98% production yield for its 5.5-reticle CoWoS in 2026 — a significantly higher baseline . This yield gap means Intel must solve an extremely hard manufacturing-ramp problem to make the 3-million-unit volume economically viable. Every percentage point of yield loss on a high-value AI accelerator costing hundreds or thousands of dollars translates directly into tens of millions in lost revenue.

Intel is ramping its Project Pelican advanced packaging complex in Malaysia, slated to become operational in 2026 . Even so, hitting multi-million-unit output at high yield for a single customer in a new technology variant (EMIB-T) would be unprecedented for Intel's foundry packaging business.

The Ironic Contradiction: Intel Drops EMIB for Its Own Flagship CPU

Perhaps the most awkward element of Google's EMIB-T bet is this: Intel's own upcoming Diamond Rapids Xeon processor will not use EMIB. According to SemiAnalysis (via LinkedIn), "Intel Abandons EMIB for UCIe in Diamond Rapids… Diamond Rapids will likely use UCIe over substrate for a long-reach die-to-die interconnect instead" . Intel showed a UCIe-based die-to-die link at ISSCC .

This creates a sharp irony: Intel is selling EMIB-T to Google as its marquee external packaging customer while abandoning it internally for its own flagship server CPU. The rationale is that for monolithic-ish CPU chiplets, UCIe over standard substrate offers sufficient bandwidth with lower cost and complexity — but the optics are awkward.

Intel is effectively asking the market to trust EMIB for Google's 3-million-unit TPU volume, yet its own premier product team chose a different interconnect standard. As SemiAnalysis put it, "Intel's 'best' packaging tech — for everyone but Intel" .

Note: The Diamond Rapids design details are drawn from industry analyst reports and LinkedIn posts from SemiAnalysis, which are credible but not official Intel confirmations .

Bottom Line

Google's EMIB-T bet is a vote of confidence in Intel's packaging at a moment when CoWoS capacity is strangled, and for very large die sizes (~10x reticle) EMIB-T offers genuine cost and scaling advantages. But Intel faces a steep yield climb (90% → 98%+) and a multi-million-unit volume ramp with a technology it has never run at that scale. The contradiction that Diamond Rapids drops EMIB underscores how Intel promotes the technology for external customers while migrating its own highest-volume product to a different standard.