This is a supply diversification strategy, not a defection. The training-focused TPU 8t reportedly retains TSMC's CoWoS-S . Intel would handle roughly half of Google's projected ~6 million total TPU volume across 2027–2028 . The move also marks a major foundry win for Intel, signaling that its advanced packaging is credible enough for a top hyperscaler, and comes as Nvidia is evaluating Intel's 18A process and EMIB packaging for next-gen GPUs .

Technical Advantages of EMIB-T Over CoWoS

Standard EMIB has been used in Intel's FPGAs and Sapphire Rapids Xeons for years, but it lacked the power delivery and reticle scaling needed for high-power AI accelerators. EMIB-T solves this by adding through-silicon vias (TSVs) directly into the embedded bridges, enabling vertical power delivery and HBM4-class support . Key architectural advantages include:

• No large silicon interposer – EMIB embeds small bridges only where dies connect, reducing material cost and simplifying the structure .
• Better thermal expansion matching – Without a large interposer spanning the whole package, coefficient-of-thermal-expansion mismatches are reduced .
• Larger reticle scaling – EMIB-T can scale beyond the ~3.3x reticle limit of CoWoS-S. Bernstein analysts estimate EMIB-T supports larger package sizes than current CoWoS offerings . Intel has stated EMIB supported 6x reticle size in 2024 and is targeting 8x in 2026 and 12x by 2028 .
• Higher theoretical yield per interposer – Because the bridges are small and localized, a defect in one bridge doesn't scrap the entire interposer, as can happen with CoWoS's large monolithic interposer .
• Available capacity – Intel's EMIB production lines are not yet fully utilized, whereas every major CoWoS slot is presold through 2027 .

The trade-off: CoWoS still leads in maximum bandwidth density and HBM proximity for the most aggressive AI designs . EMIB-T is closing the gap but has not yet surpassed CoWoS at the high end.

Scale, Yield, and the 8-Point Gap

The deal, reported by The Information and corroborated by Morgan Stanley, involves Google booking over 3 million TPU units for 2028 production . This is the challenge: Intel must deliver a technology that has never been deployed at this scale for an external customer.

Yield is the core tension. Ming-Chi Kuo first flagged that Intel's EMIB-T packaging has achieved ~90% yield in technical verification for the Humufish TPU . However, the mass production standard is ~98%, leaving a critical 8-point gap . For reference, TSMC's yield target for its 5.5x reticle CoWoS in 2026 starts from 98% . A 90% yield means 1 in 10 assembled modules is scrap; 98% drops that to 1 in 50 .

Other challenges include:

• Execution risk: Intel's Corporate VP John Pitzer admitted that earlier packaging ramp expectations for 2025 were "too optimistic" . The company is also outsourcing some EMIB production to Amkor's facility in South Korea .
• Timeline: The Humufish TPU tape-out is scheduled for ~late 2026, with production samples in H2 2027 .
• Volume scaling: Intel's 18A node capacity is expected to double by 2028, and Intel 3 fab capacity in Ireland grows 80% over the same period .

The Ironic Contradiction: Diamond Rapids

The most striking aspect of this story is that Intel is winning Google as an external EMIB customer while moving its own flagship Xeon platform away from EMIB. Intel's next-gen server CPU, Diamond Rapids (192 cores, set for 2026–2027), will likely use a UCIe die-to-die interconnect over standard organic substrate rather than EMIB . At ISSCC, Intel demonstrated a UCIe-S link running over standard organic substrate at high data rates, achieving 3x higher data rate and 2.8x higher bandwidth density than a comparable 3nm design .

This means:

• Sapphire Rapids (2023) and Granite Rapids used EMIB to stitch compute dies together.
• Diamond Rapids is expected to use a simpler, cheaper UCIe-over-substrate approach, avoiding EMIB's complexity and cost .
• Yet Intel is now selling that very same EMIB technology to Google as a premium CoWoS alternative.

The contradiction underscores that EMIB's value proposition is sharply use-case dependent: for Google's large AI accelerators, it solves a capacity shortage and offers cost-effective scaling. For Intel's own Xeons, advances in organic-substrate signaling via UCIe make the embedded-bridge approach unnecessary and too expensive for high-volume CPU packages .

This is a supply diversification strategy, not a defection. The training-focused TPU 8t reportedly retains TSMC's CoWoS-S . Intel would handle roughly half of Google's projected ~6 million total TPU volume across 2027–2028 . The move also marks a major foundry win for Intel, signaling that its advanced packaging is credible enough for a top hyperscaler, and comes as Nvidia is evaluating Intel's 18A process and EMIB packaging for next-gen GPUs .

Technical Advantages of EMIB-T Over CoWoS

Standard EMIB has been used in Intel's FPGAs and Sapphire Rapids Xeons for years, but it lacked the power delivery and reticle scaling needed for high-power AI accelerators. EMIB-T solves this by adding through-silicon vias (TSVs) directly into the embedded bridges, enabling vertical power delivery and HBM4-class support . Key architectural advantages include:

• No large silicon interposer – EMIB embeds small bridges only where dies connect, reducing material cost and simplifying the structure .
• Better thermal expansion matching – Without a large interposer spanning the whole package, coefficient-of-thermal-expansion mismatches are reduced .
• Larger reticle scaling – EMIB-T can scale beyond the ~3.3x reticle limit of CoWoS-S. Bernstein analysts estimate EMIB-T supports larger package sizes than current CoWoS offerings . Intel has stated EMIB supported 6x reticle size in 2024 and is targeting 8x in 2026 and 12x by 2028 .
• Higher theoretical yield per interposer – Because the bridges are small and localized, a defect in one bridge doesn't scrap the entire interposer, as can happen with CoWoS's large monolithic interposer .
• Available capacity – Intel's EMIB production lines are not yet fully utilized, whereas every major CoWoS slot is presold through 2027 .

The trade-off: CoWoS still leads in maximum bandwidth density and HBM proximity for the most aggressive AI designs . EMIB-T is closing the gap but has not yet surpassed CoWoS at the high end.

Scale, Yield, and the 8-Point Gap

The deal, reported by The Information and corroborated by Morgan Stanley, involves Google booking over 3 million TPU units for 2028 production . This is the challenge: Intel must deliver a technology that has never been deployed at this scale for an external customer.

Yield is the core tension. Ming-Chi Kuo first flagged that Intel's EMIB-T packaging has achieved ~90% yield in technical verification for the Humufish TPU . However, the mass production standard is ~98%, leaving a critical 8-point gap . For reference, TSMC's yield target for its 5.5x reticle CoWoS in 2026 starts from 98% . A 90% yield means 1 in 10 assembled modules is scrap; 98% drops that to 1 in 50 .

Other challenges include:

• Execution risk: Intel's Corporate VP John Pitzer admitted that earlier packaging ramp expectations for 2025 were "too optimistic" . The company is also outsourcing some EMIB production to Amkor's facility in South Korea .
• Timeline: The Humufish TPU tape-out is scheduled for ~late 2026, with production samples in H2 2027 .
• Volume scaling: Intel's 18A node capacity is expected to double by 2028, and Intel 3 fab capacity in Ireland grows 80% over the same period .

The Ironic Contradiction: Diamond Rapids

The most striking aspect of this story is that Intel is winning Google as an external EMIB customer while moving its own flagship Xeon platform away from EMIB. Intel's next-gen server CPU, Diamond Rapids (192 cores, set for 2026–2027), will likely use a UCIe die-to-die interconnect over standard organic substrate rather than EMIB . At ISSCC, Intel demonstrated a UCIe-S link running over standard organic substrate at high data rates, achieving 3x higher data rate and 2.8x higher bandwidth density than a comparable 3nm design .

This means:

• Sapphire Rapids (2023) and Granite Rapids used EMIB to stitch compute dies together.
• Diamond Rapids is expected to use a simpler, cheaper UCIe-over-substrate approach, avoiding EMIB's complexity and cost .
• Yet Intel is now selling that very same EMIB technology to Google as a premium CoWoS alternative.

The contradiction underscores that EMIB's value proposition is sharply use-case dependent: for Google's large AI accelerators, it solves a capacity shortage and offers cost-effective scaling. For Intel's own Xeons, advances in organic-substrate signaling via UCIe make the embedded-bridge approach unnecessary and too expensive for high-volume CPU packages .