IBM's 0.7nm NanoStack Chip: The First Sub-1nm Semiconductor Technology Explained

Projected performance and efficiency gains: IBM claims the new design can deliver up to 50% higher performance or up to 70% greater energy efficiency when compared to its 2 nm architecture. These are research projections, not measurements from commercial products .

SRAM scaling: 40% improvement in on-chip memory density. IBM describes this as the largest such memory gain the industry has seen in over a decade. The results were published at the 2026 Symposium on VLSI Technology .

Architecture: How NanoStack Works

NanoStack is a 3D vertical transistor architecture. Instead of continuing to shrink transistors on a flat plane (the approach used in FinFET and traditional nanosheet designs), IBM stacks nanosheet transistors vertically in three dimensions using wafer bonding .

The architecture functions as a type of complementary FET (CFET). Specifically, it stacks n-type and p-type transistors on top of each other rather than side-by-side, which saves significant die area and shortens the distances electrical signals must travel between them . IBM has described NanoStack as a "universal framework" for arranging transistors . The company has demonstrated a working prototype chip at the 0.7 nm node — the first public demonstration of functional sub-1 nm CMOS logic .

Commercialization and Business Model

IBM is explicit that the technology remains in the research stage. The company expects commercial production by its partners within roughly five years . IBM does not operate its own chip fabrication facilities. It will license the NanoStack design to manufacturing partners and foundries, a model consistent with its historical approach to commercializing semiconductor breakthroughs . The company has also mapped a longer-term roadmap toward 0.1 nm (1 angstrom) nodes .

Industry Positioning and AI Implications

IBM positions the 0.7 nm node as the first publicly disclosed sub-1 nm technology, ushering in what the industry calls the "angstrom era" of chip manufacturing . The company estimates that AI accelerators built on 7A chips could theoretically reach roughly 7,000 TOPS (trillion operations per second), compared to approximately 1,500 TOPS on current leading nodes — a roughly 4.7x improvement . IBM's announcement is widely regarded as positioning the company to compete with foundry leaders TSMC, Samsung, and Intel in the race toward angstrom-scale nodes .

Key Caveats

All performance and efficiency figures are IBM's own projections derived from a research-stage process, not shipping products. The company's five-year commercialization timeline and its dependency on licensing partners are critical constraints. As IBM's VP of global semiconductor R&D, Huiming Bu, stated at the announcement: "Nanostack is not one innovation. It is a device platform that can enable future scaling for another decade. We are getting it ready for manufacturing."