Design Partner: MediaTek's Expanding Role

MediaTek has secured an exclusive order for the Triggerfish chip . The order carries a ~30% higher unit price than the base Humufish chip , signaling a deeper collaboration that goes beyond simple component supply. Kuo notes this further validates MediaTek as Google's first-choice partner for the entire TPU v9 generation, indicating MediaTek is handling more architectural and integration work — a shift toward system-level design collaboration .

Key Technical Upgrades

Triggerfish makes three primary architectural changes compared to the current Humufish TPU v9:

• On-chip SRAM: Increased by 2–3x. This allows more of an AI agent's or RL model's active working set to stay on the chip locally, reducing the need to fetch data from slower off-chip memory. The result is lower data movement costs and improved efficiency during ultra-low-latency decoding .
• Off-chip DRAM: Upgraded from HBM4 to next-generation HBM4E. This provides higher memory bandwidth for inference at scale .
• New simulation die: A dedicated analog/simulation die is added specifically for RL and agent workloads. Possible functions include local TPU management, training/inference mode switching, and reinforcement learning with AI agent collaboration .

These changes directly target the "CPU wall" and "memory wall" bottlenecks common in AI ASICs .

Targeting AI Agents and Reinforcement Learning

Triggerfish is explicitly designed for the next wave of AI workloads: AI agents and reinforcement learning .

• Larger SRAM means more of an agent's active state — the working memory needed for multi-step reasoning — can stay on the chip, dramatically cutting latency.
• The new simulation die is a hardware accelerator optimized for the trial-and-error learning loops that define RL and agent-based systems.
• HBM4E memory ensures that when data must leave the chip, it can move at the highest possible bandwidth.

This focus aligns with Google's broader AI strategy. As noted in Google Cloud's own documentation, "The shift to Agentic AI requires infrastructure capable of multi-step reasoning and continuous reinforcement learning." TPUs are designed to "break the inference 'memory wall' by hosting massive KV caches entirely on-silicon, utilizing expanded on-chip SRAM" .

Production Timeline and Volumes

According to Kuo's supply-chain survey:

These volumes are relatively modest compared to the base TPU v9, reflecting Triggerfish's position as a targeted upgrade for specific, high-value inference workloads rather than a mass-market replacement.

How Triggerfish Fits Google's Strategy vs. Nvidia

Triggerfish is part of Google's long-running strategy to develop in-house custom silicon (TPUs) to reduce dependence on Nvidia GPUs for AI workloads .

By upgrading TPU v9 rather than waiting for a full v10, Google can iterate faster on inference-specific improvements for emerging workloads like AI agents and RL — areas where Nvidia's general-purpose GPUs may be over-engineered for pure inference .

The chip is designed for "effective compute maximization" — keeping active data on-chip to lower cost and latency, directly competing on total cost of inference against Nvidia's H100/B200-class hardware .

Key Caveats

All details are sourced from a single analyst survey (Ming-Chi Kuo, TF International Securities, June 22, 2026). Google has not confirmed the Triggerfish codename, specifications, or timeline. Pricing, volumes, and partner exclusivity remain unverified by the companies involved. Until Google makes an official announcement, this information should be treated as a credible but unconfirmed industry report.

Design Partner: MediaTek's Expanding Role

MediaTek has secured an exclusive order for the Triggerfish chip . The order carries a ~30% higher unit price than the base Humufish chip , signaling a deeper collaboration that goes beyond simple component supply. Kuo notes this further validates MediaTek as Google's first-choice partner for the entire TPU v9 generation, indicating MediaTek is handling more architectural and integration work — a shift toward system-level design collaboration .

Key Technical Upgrades

Triggerfish makes three primary architectural changes compared to the current Humufish TPU v9:

• On-chip SRAM: Increased by 2–3x. This allows more of an AI agent's or RL model's active working set to stay on the chip locally, reducing the need to fetch data from slower off-chip memory. The result is lower data movement costs and improved efficiency during ultra-low-latency decoding .
• Off-chip DRAM: Upgraded from HBM4 to next-generation HBM4E. This provides higher memory bandwidth for inference at scale .
• New simulation die: A dedicated analog/simulation die is added specifically for RL and agent workloads. Possible functions include local TPU management, training/inference mode switching, and reinforcement learning with AI agent collaboration .

These changes directly target the "CPU wall" and "memory wall" bottlenecks common in AI ASICs .

Targeting AI Agents and Reinforcement Learning

Triggerfish is explicitly designed for the next wave of AI workloads: AI agents and reinforcement learning .

• Larger SRAM means more of an agent's active state — the working memory needed for multi-step reasoning — can stay on the chip, dramatically cutting latency.
• The new simulation die is a hardware accelerator optimized for the trial-and-error learning loops that define RL and agent-based systems.
• HBM4E memory ensures that when data must leave the chip, it can move at the highest possible bandwidth.

This focus aligns with Google's broader AI strategy. As noted in Google Cloud's own documentation, "The shift to Agentic AI requires infrastructure capable of multi-step reasoning and continuous reinforcement learning." TPUs are designed to "break the inference 'memory wall' by hosting massive KV caches entirely on-silicon, utilizing expanded on-chip SRAM" .

Production Timeline and Volumes

According to Kuo's supply-chain survey:

These volumes are relatively modest compared to the base TPU v9, reflecting Triggerfish's position as a targeted upgrade for specific, high-value inference workloads rather than a mass-market replacement.

How Triggerfish Fits Google's Strategy vs. Nvidia

Triggerfish is part of Google's long-running strategy to develop in-house custom silicon (TPUs) to reduce dependence on Nvidia GPUs for AI workloads .

By upgrading TPU v9 rather than waiting for a full v10, Google can iterate faster on inference-specific improvements for emerging workloads like AI agents and RL — areas where Nvidia's general-purpose GPUs may be over-engineered for pure inference .

The chip is designed for "effective compute maximization" — keeping active data on-chip to lower cost and latency, directly competing on total cost of inference against Nvidia's H100/B200-class hardware .

Key Caveats

All details are sourced from a single analyst survey (Ming-Chi Kuo, TF International Securities, June 22, 2026). Google has not confirmed the Triggerfish codename, specifications, or timeline. Pricing, volumes, and partner exclusivity remain unverified by the companies involved. Until Google makes an official announcement, this information should be treated as a credible but unconfirmed industry report.