What did ASML announce about working with major chipmakers to adapt its latest High-NA extreme ultraviolet (EUV) lithography tools for producing large data-center chips like those designed by Nvidia and other companies, how do the current EUV and forthcoming High-NA systems diffe

ASML announced a joint industry initiative with TSMC—open to other High-NA adopters and suppliers—to transition High-NA EUV lithography from today’s 6-inch photomasks to 12-inch masks. The objective is to retain High-NA’s finer patterning while making it practical for the very large die areas used in leading data-center and AI processors, such as those designed by Nvidia. 13

Technology and capacity

• Conventional EUV scanners use a 0.33 numerical-aperture optical system and a full-field exposure area suitable for large chips; High-NA raises NA to 0.55, improving resolution, but its anamorphic optics reduce the printable field in one dimension when using the current 6-inch-mask format. The practical result is finer features but a smaller single-exposure chip area—an obstacle for the largest AI/data-center dies. 14
• ASML describes High-NA as delivering an 8 nm critical dimension; it is intended for future chip generations with still smaller features. 145
• The 12-inch-mask transition is designed to overcome that field-size/stitching constraint, so large chips need fewer stitched exposures. ASML and TSMC say it should raise fab productivity, reduce chipmaking costs, and allow manufacturers to capture more of High-NA’s benefit. 13

Who is using or assessing High-NA

• Intel is the furthest along: after experiments beginning in 2024, it began using High-NA tools for part of its Panther Lake processor production in 2026. 6
• Intel and SK Hynix were identified as planned High-NA adopters, while Intel and other chipmakers have been testing the equipment. 45
• TSMC is ASML’s formal co-leader for the 12-inch-mask initiative and expects High-NA adoption first with existing 6-inch masks, before the large-mask transition. 13
• Samsung announced expanded High-NA cooperation with ASML, plans adoption for future DRAM manufacturing, and will join the 12-inch-mask initiative. 11
• The evidence supplied does not establish firm, company-specific production dates for TSMC, Samsung, or SK Hynix beyond their stated participation, evaluation, or planned adoption. Reports that attribute 2027–28 production timing to all three are insufficiently supported here. 41135

Timeline and expected gain

• ASML and TSMC target a 12-inch-mask pilot line by 2031 and full lithography-system readiness for advanced-node production by 2033. 13
• The supplied reporting characterizes the expected productivity gain from the new large-mask approach as about 40%; ASML’s official announcement supports the direction of improvement—higher productivity and lower cost—but does not quantify it in the excerpt available here. 813
• Separately, ASML’s current-generation NXE:3800E has 220 wafers-per-hour throughput, 37% above the NXE:3600D; that is not the same as the projected large-mask High-NA gain. 1