How Huawei’s Kirin 2026 LogicFolding Uses 3D Stacking to Cut Power

Huawei’s LogicFolding is an attempt to get more performance and efficiency from physical design and 3D integration, rather than from shrinking transistors on a newer process node. For its proposed Kirin 2026 mobile processor, Huawei says it splits circuitry across two active silicon tiers and joins them face-to-face with dense hybrid bonding. The stated goal is simple: keep frequently communicating circuits closer together, so signals travel less distance. 23

The reported gains should be read as Huawei claims based on its own methodology and comparison with Kirin 9030 Pro. They are not evidence that Huawei has achieved an equivalent new lithography node or that every workload will see the same benefit. 23

What LogicFolding changes

A conventional planar chip places its logic largely across one silicon plane. As a design grows, some data and clock signals must cross increasingly long metal routes. LogicFolding instead partitions digital, analog and memory circuits between vertically stacked active layers. Hybrid bonds create a dense set of vertical connections between those tiers. 23

For Kirin 2026, reports based on Huawei’s Tau Scaling material describe a hybrid-bond pitch of roughly 1.5 micrometres and about 50 million vertical interconnects. Huawei reports transistor density rising from 155 MTr/mm² to 238 MTr/mm² under its measurement approach—roughly a 53.5% to 55% increase—while using the same process node as the Kirin 9030 Pro baseline. 35

That is why the density figure should be called effective density: the improvement comes from reorganizing where circuitry sits and how it connects, not necessarily from making each transistor physically smaller.

Why shorter wires can improve timing and power

The central engineering argument is that long metal interconnects impose resistance and capacitance. A signal on a long wire takes time to propagate and consumes dynamic energy as the wire capacitance is charged and discharged.

By moving tightly coupled logic into opposing tiers, Huawei aims to replace selected long lateral connections with much shorter vertical hops. In principle, that can:

• reduce delay on timing-critical paths;
• shorten clock-distribution routes;
• reduce the need for signal repeaters and clock buffers;
• lower interconnect capacitance; and
• create more timing margin, or enable similar performance at lower voltage.

This is the reasoning behind Huawei’s Tau (τ) Scaling framing: progress should be measured not only by transistor dimensions, but also by the time required for signals to move through a circuit and system. Huawei explicitly presents LogicFolding as a way to compress signal-propagation delay while improving density and energy efficiency.

Why Huawei focuses on data movement

Huawei is not claiming that transistor switching has no energy cost. Its point is that, in large modern processors, moving data and distributing clocks can consume a substantial share of dynamic power. Every long traversal of a metal route, and every buffer inserted to drive that route, adds switching activity.

This makes physical locality especially important. If a producer of data and the block consuming it can be placed closer together, the chip can spend less time and energy transporting signals between them. LogicFolding is therefore a locality strategy as much as a packaging strategy. 2

Kirin 2026: Huawei’s reported gains

Huawei’s reported comparison with the Kirin 9030 Pro is an iso-performance claim: the company says the new architecture can reduce total power consumption by 41% at comparable performance, while increasing measured transistor density by about 55%. It also reports a 5.6% reduction in power density under the stated operating conditions. 47

Reports of Huawei’s material also describe larger claimed savings in highly parallel subsystems: 66% lower NPU power, 58% lower GPU power, and 41% lower CPU big-core power versus the prior planar design under the cited comparison. 1

The pattern makes architectural sense. NPU and GPU designs often contain many regular, communication-intensive units, which may offer more opportunities to co-locate producers, consumers and local storage across tiers. A CPU can benefit from shorter paths too, but it has a more constrained dependency structure.

Why serial CPU work is harder to accelerate

A CPU frequently runs serial instruction streams: one operation may depend on the output of the one before it. That dependency chain limits how freely a workload can be divided across physical regions of a chip.

3D placement can still reduce some wire and clock costs, but it cannot eliminate the fundamental need to wait for dependent results. That helps explain why Huawei’s reported CPU power reduction is smaller than its reported NPU and GPU reductions. 1

The engineering trade-offs: heat, yield and cost

Stacking active logic brings difficult implementation problems. Heat must be removed from densely packed active layers, while power delivery, testing, repair and debug become more complicated. Wafer alignment and bond defects can also affect manufacturing yield, and a multi-tier design can add process and packaging cost.

Those constraints are important because the value of 3D integration depends on usable, reliable volume production—not just an attractive physical-design result. Reuters characterized Huawei’s broader approach as a potential route around some limitations imposed by sanctions, while noting that whether it amounts to a true breakthrough remains unresolved.

What Huawei projects for Kirin 2027

Huawei’s next roadmap step is more aggressive: a 1 µm hybrid-bond pitch and more than 100 million vertical interconnects for Kirin 2027. It has also described a 47% iso-performance power reduction target and a longer-term 720 nm top-metal-pitch goal while retaining more than 100 million vertical links. These are forward-looking targets, not independently verified shipping-product results. 15

A finer bond pitch could make vertical connections useful for a larger fraction of a chip’s logic, but it also raises the demands on alignment, defect control, design tools, thermal management and test.

What this means under export restrictions

LogicFolding is strategically appealing because it seeks improvements without depending solely on access to the newest lithography equipment. But it does not make manufacturing constraints disappear. Advanced semiconductor export controls continue to cover categories of chips, equipment and related technology relevant to advanced-node production in China.

Huawei’s 3D approach should therefore be understood as a complementary scaling path: it may extract more capability from a given process technology, but it still requires sophisticated bonding, metrology, design automation and manufacturing execution.

Bottom line

Huawei’s Kirin 2026 proposal reframes chip scaling around shorter signal travel. Two hybrid-bonded active tiers could increase placement density and reduce the delay and energy associated with long interconnects—particularly in parallel, data-moving blocks such as NPUs and GPUs.

The headline figures—about 55% higher effective transistor density and 41% lower power at comparable performance—remain Huawei-reported claims. The real test will be whether the architecture can meet its promised efficiency, thermal, yield and cost targets in shipping mobile processors at scale. 237