How Synopsys, Cadence, and Siemens Are Competing to Make Chip Design Agentic

DAC 2026 made agentic AI a platform-level contest in electronic design automation (EDA). Synopsys, Cadence, and Siemens EDA are no longer presenting AI only as a conversational assistant for writing RTL or searching documentation. Their emerging systems are designed to decompose engineering objectives, invoke established EDA tools, interpret measurements, and repeat the loop until a target is reached. 217

That changes the strategic question. The leading vendor may not be the one with the most capable general-purpose model, but the one that can connect an agent to design data, deterministic solvers, verification evidence, security controls, and production signoff.

What changed at DAC 2026?

Traditional EDA tools execute well-defined operations: synthesis, simulation, formal verification, place-and-route, timing analysis, or physical signoff. An agentic EDA system adds a planning and coordination layer around those tools.

In a typical loop, the agent:

1. interprets a design objective or failure;
2. selects the relevant tools and sub-tasks;
3. generates or changes RTL, constraints, tests, or configurations;
4. runs deterministic simulations, formal checks, or physical analysis;
5. reads the resulting metrics, logs, waveforms, or counterexamples; and
6. proposes another change and repeats the process.

Research on agentic physical design describes a similar pattern: interpreting natural-language objectives, invoking EDA tools, analyzing their outputs, modifying configurations or source code, and iterating against measured quality of results. 1

The distinction from a copilot is important. A copilot suggests the next action; an agentic workflow can own a longer sequence of actions while remaining bounded by engineering tools and human-defined goals.

Synopsys: an autonomy ladder built around AgentEngineer

Synopsys’ strategy is organized around an L1–L5 autonomy progression. The basic idea is to move from assistance and guided automation toward increasingly independent engineering workflows, eventually spanning multiple design domains. The exact boundary between levels is a roadmap rather than an industry-wide standard, so the levels should be read as Synopsys’ framework for measuring autonomy, not as a universal certification scheme.

The practical centerpiece is AgentEngineer. At DAC, Synopsys described an orchestrator that can break a verification objective into smaller jobs, coordinate specialized agents, call EDA tools, inspect results, and continue working through a closed loop. Synopsys and NVIDIA described these as fully autonomous, long-running workflows for chip and electronics-system design. 314

Synopsys highlighted autonomous verification, root-cause analysis, and debug closure. Company-reported demonstrations claimed up to 50 times faster time to validated RTL and a 20% coverage improvement; those figures are vendor claims rather than independent benchmark results. 19

A separate Synopsys workflow developed with Microsoft Discovery reported preliminary reductions of 25% to 40% in debug-cycle time. That result should also be treated as an early evaluation, not a general production benchmark. 17

From RTL to thermal simulation

Synopsys is extending the same agentic concept beyond digital logic. Its DAC strategy includes physics-heavy electronic-system workflows such as thermal simulation, where an agent can help set up a simulation, execute it, assess the output, and refine the workflow. The broader “silicon-to-systems” positioning is strengthened by Synopsys’ Ansys portfolio and reaches beyond an RTL-to-GDS flow. 1417

The strategic advantage is breadth: if the same orchestration layer can operate across verification and system-level physics, Synopsys can present agentic EDA as a continuous engineering environment rather than a collection of isolated assistants.

Cadence: specialist agents plus persistent design context

Cadence is taking a different route. Its public positioning centers on a hierarchy of specialist agents coordinated by a higher-level AI super-agent, associated with the ChipStack AI Super Agent and reporting that refers to AgentStack or AuraStack. The naming is not consistently corroborated across the available materials, so AgentStack and ChipStack AI Super Agent are the safer references. 218

Cadence’s most distinctive concept is the Mental Model. Rather than relying only on the immediate prompt, the agent is intended to maintain structured, design-specific context: the project’s constraints, history, intent, and accumulated decisions. That matters because chip design is highly contextual. A locally reasonable change can violate a timing budget, packaging constraint, power target, or earlier architectural decision.

Cadence is also emphasizing multiphysics acceleration. Its pitch is to let agents reason across electrical, thermal, mechanical, and fluid effects, so a design decision can be evaluated against system-level consequences rather than only digital metrics. 1718

In strategic terms, Cadence is competing through architectural completeness and context. The goal is not merely to automate one stage, but to make the agent understand the design as a persistent system with interacting constraints.

Siemens: trust through self-verification

Siemens EDA is differentiating its Fuse EDA AI Agent around trust. The core idea is a self-verification loop in which an agent’s proposed action is checked against deterministic, physics-based Siemens engines before the result is allowed to move forward. 2

Fuse is built around a scalable Model Context Protocol (MCP) architecture. MCP provides a common way to connect an orchestration layer to tools and engineering information across areas such as RTL, verification, analog and custom design, place-and-route, and physical signoff. 2

This approach addresses one of the central risks of autonomous engineering: a language model can produce a plausible plan that is physically invalid. In a self-verifying workflow, the authoritative check comes from the domain tool. If timing, geometry, physics, or another formal constraint rejects the proposed action, the workflow can use that evidence to revise its plan.

Siemens also presents a broader digital-thread opportunity. Its agentic vision can connect design decisions with manufacturing planning and supply-chain scheduling, extending the workflow beyond chip implementation itself. The differentiator is therefore not only autonomy, but autonomy constrained by industrial evidence and downstream execution.

NVIDIA is becoming the common infrastructure layer

NVIDIA is not replacing the EDA incumbents as a conventional EDA vendor. Instead, it is supplying several layers that can support the new agentic stack—and creating a potential point of platform dependence in the process.

NVIDIA invested $2 billion in Synopsys as part of an expanded multiyear partnership focused on AI-driven engineering and accelerated EDA workloads. 13

The infrastructure spans several functions:

• Accelerated computing: Grace Blackwell is being used for simulation and AI inference. Synopsys reported that NVIDIA NIM inference microservices delivered twice the time-to-information for its generative-AI Copilot, while NVIDIA reported a 34-times CPU-comparison speedup for a Fluent aerodynamic-simulation use case. These are reported use-case results, not universal EDA benchmarks. 1516
• Models and orchestration: Synopsys’ DAC workflow used NVIDIA Nemotron, the NVIDIA Agent Toolkit, and the OpenShell runtime for agent execution and governance. 314
• Physics acceleration: NVIDIA’s CUDA-X and PhysicsNeMo libraries are intended to support simulation-heavy engineering workflows. 2
• CPU performance: Vera CPU targets compute-intensive and sequential workloads that remain important in conventional EDA. NVIDIA says it is working with Cadence and Synopsys to optimize applications; reported testing showed about 1.5-times performance gains for Cadence Jasper and Synopsys VCS, though those figures are vendor-reported. 45

The result is a layered contest. EDA companies own design databases, domain tools, and signoff flows; NVIDIA supplies compute, models, orchestration components, and runtime infrastructure. Customers may benefit from faster workflows, but the arrangement also raises questions about how much of the future engineering stack will depend on a common hardware and software platform.

What the Kimi K3 experiment proves—and what it does not

The Kimi K3 demonstration is a useful counterpoint to the incumbent announcements. The supplied account describes a 48-hour autonomous run in which Kimi K3 designed, optimized, and verified a chip for a nano model using open-source EDA tools and the Nangate 45 nm library. The reported design occupied about 4 mm² and closed timing at 100 MHz in simulation. 17

That is meaningful evidence that an LLM-based agent can coordinate a constrained end-to-end design loop. It shows that architecture, RTL generation, optimization, verification, and timing analysis can be connected into one autonomous process under favorable conditions.

It is not evidence that commercial EDA tools or expert chip-design teams are obsolete. The experiment used a mature 45 nm reference flow, roughly two decades behind leading-edge process technology. It does not establish performance on modern process design kits, advanced timing and power closure, analog design, design-for-test, IP integration, reliability analysis, manufacturing constraints, or production signoff.

The experiment also exposes an evidence problem. The reported result is a technical demonstration from the project’s own materials, not an independently reproduced production benchmark. Claims that the design performs 20 to 30 times worse than contemporary chips should therefore not be treated as a controlled comparison without stronger evidence.

The careful conclusion is narrower: open-source tools can support an impressive mature-node demonstration, while competitive and manufacturable leading-edge designs still depend heavily on foundry collateral, process libraries, mature signoff flows, and specialized engineering expertise.

Why this creates an opening for Chinese EDA vendors

Agentic AI gives Chinese EDA companies an opportunity to compete at the workflow level rather than simply reproduce every mature point tool. The opportunity is particularly strong in verification, debugging, domestic deployment, advanced packaging, and LLM-native interfaces. Reporting from DAC describes agentic AI entering the flow from RTL generation and testbench creation through simulation, formal verification, and debugging. 17

Examples in the supplied research include:

• Xpeedic, whose signal- and power-integrity capabilities could be paired with agentic system, package, and advanced-packaging analysis.
• XEPIC, which announced the XEPIC Intelligent System foundation, including intelligent verification and design systems and a faster simulation offering. 17
• UniVista, which has described an agentic design platform capable of coordinating RTL design, verification, correction, and optimization on a domestically developed EDA architecture. 17
• Chips Z, Banxin, and Zhiwei Chuangxin, which illustrate the broader push toward domestically controlled toolchains, specialized design and verification agents, and LLM-native engineering interfaces.

The most defensible product pattern is an evidence loop: generate a hypothesis or fix, run simulation or formal verification, inspect the counterexample or quality metric, and feed that evidence back to the agent. This is more credible than asking a general-purpose model to generate a chip and trusting the output without domain checks.

The often-repeated estimate that engineers spend about 60% of their time on debugging and process-heavy work should be treated as an industry estimate, not a universal measurement. But the underlying opportunity is clear: repetitive triage, trace analysis, test creation, root-cause localization, and regression repair are attractive targets for automation. 17

The real EDA competition is over evidence

DAC 2026’s most important signal was not that autonomous chip design is already solved. It was that the major EDA vendors now see agentic workflows as the next way to extend their platform advantages.

Synopsys is emphasizing an autonomy ladder, AgentEngineer, verification closure, and silicon-to-systems breadth. Cadence is emphasizing specialist-agent coordination, persistent design context, and multiphysics reasoning. Siemens is emphasizing self-verification, MCP-based tool integration, and a wider industrial thread.

Their common challenge is trust. A useful EDA agent must be able to explain what it changed, reproduce the workflow, preserve design intent, and show deterministic evidence that the result satisfies the relevant constraints.

The near-term winner is therefore unlikely to be the vendor with the most fluent model. It will be the one whose agents can operate safely inside existing data, IP, security, simulation, and signoff flows—and turn every autonomous action into auditable engineering evidence.