Huawei’s Tau Scaling Is a Breakthrough, Jensen Huang Says. So Why Isn’t TSMC Worried?

Jensen Huang’s assessment of Huawei’s new chip strategy was notably measured: the Tau (τ) Scaling Law is a significant breakthrough for Huawei, but it does not currently pose a threat to TSMC. His reasoning was straightforward: Huawei is applying a promising 3D integration strategy to a problem that TSMC and other major chipmakers have been working on for years. 6713

That distinction matters because Huawei’s announcement has sometimes been interpreted as proof that the company has reached 2nm, 1nm, or even 1.4nm manufacturing. The available evidence supports a narrower conclusion. Huawei has proposed a way to improve effective transistor density and signal speed without relying entirely on further lithographic shrinking—but the approach still needs to demonstrate its performance, yield, thermal management, and economics at scale. 1317

What Huawei’s Tau Scaling Law is designed to change

Traditional semiconductor scaling is primarily associated with making transistors smaller. Huawei’s Tau Scaling Law instead puts the emphasis on reducing the time signals take to travel through devices, circuits, chips, and complete computing systems. The Greek letter τ refers to this propagation delay. 25

The architectural technique Huawei introduced alongside the principle is called LogicFolding. It reorganizes circuits that would traditionally be arranged in a flat, two-dimensional layout into more tightly connected vertical structures. The stated goal is to bring logic, analog, and memory functions closer together, shortening critical signal paths and improving effective density without requiring an entirely new transistor process node. 127

Reports describing Huang’s comments say the approach uses chiplet stacking and hybrid bonding to increase the number of transistors in a chip—potentially doubling, tripling, or even quadrupling the count—without making the semiconductor line width smaller. These are reported capabilities of the proposed approach, not independently verified results from a shipping product. 612

Why Huang called it a breakthrough for Huawei

For Huawei, the appeal is strategic as well as technical. An architecture that extracts more performance or density from existing manufacturing processes could offer the company another route forward while access to some advanced chipmaking tools remains restricted. Huawei has said that its high-end chips could reach transistor density equivalent to a 1.4nm process by 2031. 417

If achieved, that would be an important development. It would show how system architecture, interconnects, and packaging can supplement transistor scaling as physical shrinking becomes more difficult—or less accessible.

But “1.4nm-equivalent” does not mean that Huawei is manufacturing transistors on a genuine 1.4nm process. The claim refers to transistor-density equivalence. Available reporting says Huawei has not provided independent data showing that future chips would match the overall performance, power efficiency, yield, reliability, or production consistency of a leading-edge 1.4nm-class process. 1317

Why he said Tau Scaling was not a threat to TSMC

Huang’s comparison was mainly about technological maturity and execution. TSMC has spent years developing die stacking, 3D integration, and advanced packaging as complements to conventional transistor scaling. Reports of Huang’s remarks say he pointed out that TSMC and Taiwan had possessed related technology for about a decade. 71213

TSMC offered a similar assessment, describing Huawei’s proposal as “3-D scaling, not revolutionary.” The company also emphasized that advanced packaging, chip stacking, and other integration methods are becoming increasingly important alongside continued improvements in transistor density.

This does not make Huawei’s work irrelevant. It means that LogicFolding is not automatically a replacement for TSMC’s process technology or manufacturing ecosystem. TSMC can combine smaller transistors with advanced packaging, while Huawei is presenting vertical integration as a more central alternative to continued geometric shrinking.

The competitive question, then, is not whether 3D integration exists. It is who can design, manufacture, bond, test, achieve acceptable yields, and scale the complete system reliably and economically.

The hardest engineering problems are still ahead

Stacking can shorten signal paths, but adding vertical layers introduces difficult engineering challenges. Heat must be removed from a denser structure. Bonding and post-processing must achieve high yields. Designers must also verify and test a more complex system. EDA workflows, thermal management, repairability, and mass production can all become more complicated as more functions are integrated vertically. 136

These issues matter because Huawei’s most visible near-term milestone is still a plan. The company has said that Kirin smartphone chips using a Tau Scaling architecture called LogicFolding are scheduled for autumn 2026. However, reports note that the product has not yet produced independently benchmarked results or established a confirmed high-volume manufacturing record. 317

What to watch next

The first meaningful test will be whether a LogicFolding-based Kirin chip delivers measurable benefits in a real product rather than only in architectural projections. The most useful evidence will include:

• independent performance benchmarks;
• power-consumption measurements;
• sustained thermal performance;
• manufacturing-yield data; and
• proof that Huawei can produce the design at commercially meaningful volume.

The longer-term test will be Huawei’s 2031 density target. Even if the company reaches 1.4nm-equivalent transistor density, that achievement should be assessed separately from the process-node label. Chip performance depends on more than transistor count. Interconnect delay, memory access, power delivery, cooling, software, packaging quality, and manufacturing consistency all matter.

The bottom line

Huang’s reported position can be summarized in one sentence: Huawei’s Tau Scaling Law may be a major breakthrough for the company because it offers a credible alternative path to higher chip density and faster signal movement, but it is not yet a near-term displacement threat to TSMC’s leading-edge manufacturing and packaging capabilities. 613

The fairest reading is not that Huawei has already achieved 2nm, 1nm, or 1.4nm manufacturing. It is that Huawei has proposed a 3D architectural strategy that could extract more usable performance from less advanced manufacturing—and now has to prove that strategy through independent results and reliable mass production. 1317