Huawei presented its Tau (τ) Scaling Law at IEEE ISCAS 2026, proposing that time scaling—especially lower signal propagation delay—should complement or replace conventional geometric scaling. The company says its LogicFolding architecture has supported the mass production of 381 smartphone and AI chips over six year...
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Create a landscape editorial hero image for this Studio Global article: What did Huawei announce about achieving advanced semiconductor production without TSMC, including He Tingbo’s appearance at the IEEE Intern. Article summary: Huawei announced a proposed route to more advanced chips that emphasizes design and system architecture rather than relying solely on ever-smaller lithographic features. It is a significant strategic claim, but not proof. Topic tags: general, general web, user generated, government, education. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, wat
Huawei has outlined an alternative route to more advanced processors: improve the way chips are designed and connected so that performance gains do not depend entirely on making transistors smaller.
The announcement is strategically important, but it should not be read as evidence that Huawei—or its domestic manufacturing partners—can already produce a genuine leading-edge 1.4nm chip without TSMC. Huawei is describing a design and systems roadmap, and its most ambitious performance and density projections remain company claims rather than independently verified manufacturing results.
At the 2026 IEEE International Symposium on Circuits and Systems in Shanghai, Huawei semiconductor chief He Tingbo delivered a keynote titled “New Semiconductor Path in Practice.” She presented what Huawei calls the Tau (τ) Scaling Law, which proposes shifting the industry’s focus from traditional geometric scaling to time scaling. 1
In conventional chip development, progress has largely been associated with reducing transistor dimensions and moving to smaller process nodes. Huawei’s approach instead emphasizes reducing the system time constant, particularly the delay involved in moving signals through devices, circuits, chips and larger computing systems.
The aim is to optimize several layers together—from transistor and interconnect design to circuit layout, chip architecture and system-level communication—so that computing tasks are completed more quickly and efficiently. 12
Huawei identifies LogicFolding as a central technology within this strategy. The company says the architecture can move beyond the limitations of conventional planar layouts by shortening critical signal paths and reducing the resistance and capacitance that create propagation delays. 2
In practical terms, the approach seeks to place and connect logic more efficiently, increasing the number of useful transistors in a given area while also improving performance and energy efficiency. It is therefore a design-level method for extracting more capability from an available manufacturing process, rather than a replacement for fabrication technology itself.
Huawei says the broader Tau-based methodology has already been used in the design and mass production of 381 chips for smartphones and AI-computing applications over the past six years. The company also said that a new Kirin smartphone processor scheduled for autumn 2026 will use LogicFolding fully. 14
Huawei’s most eye-catching projection is a goal of reaching transistor density equivalent to a 1.4nm, or 14A-class, process by 2031. 18
That wording is important. A claim of “1.4nm-equivalent density” does not necessarily mean Huawei or a Chinese foundry will be etching transistors with the same manufacturing technology used for a literal 1.4nm process. Chip density and real-world performance can also improve through circuit architecture, interconnects, packaging and software-hardware co-design.
The distinction is similar to comparing a car’s engine size with its overall performance: a smaller engine does not automatically determine how quickly or efficiently the whole vehicle operates. Likewise, a process-node label alone does not capture every factor affecting a modern processor.
Huawei has also publicized substantial density improvements for early LogicFolding implementations, but those figures have not been independently audited in the available reporting. 45
The roadmap comes against the backdrop of Huawei’s loss of access to Taiwan Semiconductor Manufacturing Company, or TSMC, following U.S. restrictions. Those controls sharply limited Huawei’s access to advanced foreign-made chips and constrained China’s ability to obtain some of the equipment needed for next-generation semiconductor production. Reporting in 2025 indicated that China’s leading foundry, Semiconductor Manufacturing International Corporation (SMIC), was still struggling to move to newer production generations. 14
The restrictions severely damaged Huawei’s smartphone business, particularly its ability to offer competitive 5G flagship devices. A visible turning point came in 2023 with the Mate 60 Pro, which used a domestically produced, 7nm-class processor made by SMIC. That chip enabled Huawei to return to the 5G flagship market and demonstrated that the company could build at least a partial domestic alternative to its former supply chain. 2
LogicFolding represents a continuation of that strategy. Instead of trying to reproduce TSMC’s most advanced fabrication capability immediately, Huawei is seeking to obtain more performance and effective density from manufacturing resources that remain available domestically.
Huawei’s announcement is best understood as a proposal for post-geometric scaling: use architecture, circuit design and system optimization to keep improving chips as conventional transistor shrinkage becomes more difficult and expensive.
If the company’s claims hold up in commercial products, LogicFolding could help Huawei narrow some of the practical performance gap created by restricted access to advanced fabrication tools. The planned 2026 Kirin processor will be an important early test of whether the concept delivers measurable benefits outside presentations and technical papers.
For now, however, Huawei is not claiming that it has already replicated TSMC’s most advanced fab technology. Its claim is narrower—and potentially more significant in the long term: architecture-level innovation could allow constrained domestic manufacturing to produce chips with performance and density approaching much smaller process nodes, with a 1.4nm-equivalent target by 2031.
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Huawei presented its Tau (τ) Scaling Law at IEEE ISCAS 2026, proposing that time scaling—especially lower signal propagation delay—should complement or replace conventional geometric scaling.
Huawei presented its Tau (τ) Scaling Law at IEEE ISCAS 2026, proposing that time scaling—especially lower signal propagation delay—should complement or replace conventional geometric scaling. The company says its LogicFolding architecture has supported the mass production of 381 smartphone and AI chips over six years, with a fully LogicFolding based Kirin processor planned for autumn 2026.
Huawei’s 2031 goal is transistor density equivalent to a 1.4nm or 14A class process—not proof that it already has a true 1.4nm manufacturing node independent of TSMC.