Huawei’s 1.4nm-equivalent chip plan: how LogicFolding aims to bypass EUV

Huawei’s May 2026 announcement was an ambitious chip-design and packaging roadmap—not proof that China can already manufacture true 1.4nm transistors. The company paired a three-dimensional circuit architecture called LogicFolding with a proposed Tau (τ) Scaling Law, claiming that the approach could deliver transistor density equivalent to a 1.4nm process by 2031 without relying on extreme ultraviolet (EUV) lithography. 12

What Huawei announced

At the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, Huawei semiconductor chief He Tingbo presented the Tau Scaling Law and LogicFolding. The law is sometimes informally called “He’s law” or “Her’s Law”—a play on He’s surname—but Huawei’s official name is the Tau Scaling Law. 12

Huawei said an initial double-layer implementation would be introduced in a Kirin processor in 2026. A three-layer version is projected to reach the company’s stated 1.4nm-equivalent transistor density by 2031. 13

The important qualification is the word equivalent. Huawei is not saying that its manufacturing partners will etch every transistor at a literal 1.4nm node. It is claiming that a different physical arrangement of logic could produce comparable transistor density and potentially similar system-level capabilities.

How LogicFolding is supposed to work

Traditional semiconductor scaling has largely followed the logic associated with Moore’s Law: make transistors smaller, place more of them on a chip and improve performance. As shrinking becomes increasingly difficult and expensive, Huawei says the industry should focus less on transistor dimensions and more on the time it takes signals to move through a circuit.

That is the central idea behind Tau scaling. The Greek letter τ represents a time constant—in this context, the delay created as signals encounter resistance and capacitance along their path. Shorter connections can reduce those interconnect penalties, allowing data to move more quickly and potentially improving performance per watt.

LogicFolding is the architectural method Huawei proposes to achieve that goal. Instead of laying logic across a single two-dimensional plane, the design reorganizes and stacks circuit elements vertically. Folding the layout can shorten critical signal paths and use chip area more efficiently. Huawei has claimed an approximately 55% stepwise gain in transistor density from the approach. 24

In simple terms, the strategy is to change the shape and arrangement of the circuit when shrinking the transistor itself becomes harder. The transistor does not necessarily become smaller; the distance and time between important parts of the circuit are reduced.

Why the approach could lessen dependence on EUV

EUV scanners, including those made by ASML, are used to pattern some of the smallest features in advanced chips. China cannot obtain ASML’s most advanced EUV machines under export controls, making conventional progress toward the leading process nodes more difficult. 1

Huawei’s proposal is to extract more computing capability from older or more accessible manufacturing processes by combining them with advanced three-dimensional design and packaging. If successful, that could reduce the amount of geometric shrinking required to achieve a given level of density or performance.

But this would not make EUV irrelevant. LogicFolding could change how much performance is obtained from a given manufacturing process, while EUV and other process technologies would still affect feature size, power, yield and cost. The phrase “1.4nm equivalent” should therefore be read as a density comparison, not as confirmation of a literal 1.4nm fabrication node. 13

How it compares with China and TSMC

China’s demonstrated domestic leading-edge production has generally been characterized as 7nm class, using older deep ultraviolet lithography rather than EUV. Huawei’s roadmap is therefore an attempt to bridge several nominal process generations through architecture, stacking and system-level optimization rather than conventional feature shrinkage. 15

TSMC is pursuing the conventional process-scaling route alongside advanced packaging. The company has 2nm technology and has said it aims to begin 1.4nm production in 2028—roughly three years before Huawei’s 2031 target for 1.4nm-equivalent density. 15

The comparison is not perfectly like-for-like. TSMC’s figures refer to manufacturing process technology, while Huawei’s target refers to the density and capabilities it says can be achieved through a new design approach. A nominal node number alone does not establish that two chips will have the same speed, energy efficiency or real-world AI performance.

Why the breakthrough claim remains unproven

Huawei did not provide independently verified benchmarks, production-chip measurements, yield data, power figures, reliability results or cost data for a commercial LogicFolding implementation. Reuters therefore reported that whether the proposal represents a genuine breakthrough remains unresolved. 12

Density is only one part of chip performance

Higher transistor density does not automatically deliver a faster or more efficient product. Whole-chip performance also depends on:

• clock speed and latency;
• power consumption and delivery;
• memory bandwidth and capacity;
• input/output connections;
• packaging quality;
• manufacturing yield and reliability; and
• software and system support.

A three-dimensional structure may shorten selected paths, but it can also make routing, clock distribution, testing and power delivery more complicated.

Heat could become a major obstacle

Stacking active logic concentrates heat and makes it harder to remove heat from inner layers. That challenge is especially important for sustained, high-power workloads such as AI acceleration. Analysts have identified thermal management, electronic design automation (EDA) tools and manufacturing yields as significant hurdles. 6

Power delivery and clocking may also become more difficult when multiple active layers operate in close proximity. A design that looks attractive on a density diagram could lose its advantage if it must run at lower power or speed to remain thermally stable.

The design-tool chain is not yet demonstrated

LogicFolding would require EDA systems capable of jointly optimizing three-dimensional placement, routing, timing, verification, thermal behavior, power delivery and testing. Conventional two-dimensional design flows are not necessarily suited to that task.

Even if the architecture works in principle, advanced stacking can add process steps, packaging complexity and opportunities for defects. Lower yields and higher manufacturing costs could offset the nominal density benefit. The evidence available so far does not show that Huawei has solved those system-level problems. 26

Huawei’s wider sanctions strategy

The announcement is Huawei’s clearest public attempt to turn technology restrictions into a reason to pursue a different development path. Instead of waiting for access to EUV equipment, leading U.S. EDA tools or Nvidia’s most advanced products, the company is seeking domestic alternatives across chip design, manufacturing, packaging and AI computing. That strategy fits China’s broader push for semiconductor self-reliance. 12

Huawei’s 2023 Mate 60 comeback was an earlier milestone. The smartphone used a domestically made 7nm-class Kirin chip and demonstrated that sanctions had not ended Huawei’s ability to rebuild its mobile-chip business. The Tau and LogicFolding roadmap extends that recovery story from one flagship product to a longer-term smartphone and AI-chip strategy. 12

Nvidia’s reduced position in China raises the stakes. Export controls have restricted Chinese access to the company’s most advanced AI accelerators, creating more room for Huawei and other domestic suppliers. Still, Huawei’s dominance is not guaranteed, and Chinese competitors remain active in the market. 78

Chinese commentary has broadly framed the announcement as evidence that external restrictions can encourage domestic innovation and competition. That political interpretation should be kept separate from technical validation: positive reactions cannot replace independent evidence on performance, power, cost, yield and reliability. 12

What the announcement does—and does not—show

Huawei has proposed a plausible-sounding alternative to relying exclusively on smaller transistors: stack logic, shorten signal paths and optimize the full system around propagation time. If it can be manufactured economically at scale, the approach could help China obtain more computing capability from equipment that remains accessible under export controls.

But the May announcement was still a roadmap and a set of company claims. It did not demonstrate a production chip with independently verified 1.4nm-equivalent performance. The decisive tests will be commercial: whether Huawei can deliver working products, maintain acceptable yields, control heat and power, support them with adequate design tools, and compete on cost and software.

The specific evidence provided here is also insufficient to attribute a single authoritative Chinese official reaction about U.S.–China AI cooperation directly to the LogicFolding announcement. The broader policy tension is clear—China is pursuing technological self-reliance while both countries face incentives to manage AI risks—but this announcement is principally a semiconductor-competition story, not proof of a settled framework for AI cooperation.