Huawei’s alternative route beyond the lithography race

Huawei is trying to change the question at the heart of processor development. Instead of asking only how much smaller transistors can become, the company is asking how quickly signals, data and computing tasks can move through an entire system.

That idea is central to Huawei’s Tau Scaling Law, introduced in May. The approach targets the time constant, represented by the Greek letter τ, associated with signal propagation and system delays. It does not make semiconductor physics—or the importance of advanced manufacturing—disappear. Rather, it shifts some of the performance race toward interconnects, memory access, packaging, architecture and software coordination.

From geometric scaling to time scaling

For decades, the semiconductor industry’s main route to higher performance was geometric scaling: shrinking transistors so that more of them could fit into a given area while improving speed and efficiency. That strategy is becoming increasingly difficult as manufacturing approaches physical and economic limits. At the same time, US export controls have restricted China’s access to ASML’s most advanced extreme ultraviolet, or EUV, lithography equipment.

Huawei’s proposed response is to optimize the time required for information to travel through a chip and across a larger computing system. Its LogicFolding architecture is intended to shorten critical wiring and integrate logic, analogue and memory elements more tightly, reportedly using a more vertically integrated design.

The potential advantage is strategic as much as technical. If more performance can be extracted from architecture and system design, China may be able to reduce—though not eliminate—its dependence on the most advanced lithography tools.

What the September smartphone chip will show

Huawei is expected to introduce a Kirin smartphone processor using LogicFolding in September. That launch will be a useful commercial test, but it will not by itself prove that the company has replaced EUV lithography or overturned the economics of transistor scaling.

Researchers and industry analysts will need to examine several details:

• the chip’s actual manufacturing process and production yield;
• CPU, GPU and neural-processing performance;
• sustained performance rather than short peak benchmark scores;
• power consumption, heat dissipation and battery impact;
• packaging, memory bandwidth and interconnect design; and
• real-world performance against leading smartphone processors.

A strong result would demonstrate that architecture and integration can narrow the performance gap even when access to leading-edge manufacturing is constrained. It would not establish that Huawei has escaped the underlying limits of semiconductor fabrication. Claims that the design could deliver an advanced process-equivalent density therefore require careful distinction between density equivalence and production on the corresponding physical process node.

The 18-story pagoda versus the five-layer cake

Huawei semiconductor chief scientist Liao Heng has offered a broader way to understand the challenge through an 18-story pagoda model of the AI value chain. The metaphor expands on NVIDIA CEO Jensen Huang’s “five-layer cake,” which describes AI at a high level as five linked layers: energy, chips, computing infrastructure, cloud and AI models, and applications.

Huang’s model is an industrial map. It shows how energy supports chips, chips support infrastructure, infrastructure supports models, and models ultimately enable applications and economic value.

Liao’s pagoda is more granular and engineering-focused. It exposes the dependencies hidden within those broad categories: theory, energy, mining and raw materials, silicon, transistor and process design, wafer fabrication, lithography and equipment, advanced packaging, chip architecture, compilers and runtimes, operator partitioning, quantization, training methods, foundation models, inference, agents, products and commercial applications.

The difference is not simply that one structure has five levels and the other has 18. Huang emphasizes the industrial stack and where value is created; Liao emphasizes the many technical and production interfaces that must work together to deliver a functioning AI system.

Why the weakest layer sets the ceiling

Liao’s “shortest layer” argument is essentially a case for end-to-end systems engineering. A powerful accelerator cannot compensate for insufficient electricity, memory bandwidth, poor packaging, low fabrication yields, weak compiler support, slow networking or software that leaves processors idle.

In practice, throughput, cost and reliability are often limited by the weakest dependency. Improving one layer while neglecting another can therefore produce diminishing returns. The pagoda model argues for stronger coordination across the full chain rather than treating a faster chip as a complete solution.

This also explains Huawei’s interest in cross-layer collaboration. The company’s strategy is not limited to designing a processor; it involves coordinating chip architecture, memory, networking, compilers, runtimes, quantization and distributed-training software.

Can clusters make up for weaker individual chips?

One possible answer is to combine larger numbers of domestically available accelerators. A cluster of individually less capable chips can still deliver useful system-level performance if its hardware and software are co-designed to minimize communication, synchronization and idle time.

That strategy is most promising for workloads that divide efficiently across many processors. It also carries costs. More chips can mean higher power consumption, greater cooling and networking requirements, more complicated software, and additional operational overhead. A cluster built from weaker accelerators is not automatically equivalent to a system using fewer frontier GPUs.

Available reporting supports coordinated clusters and cross-layer optimization as part of Huawei’s strategic direction, but independent evidence remains insufficient to establish parity with leading NVIDIA systems.

China’s domestic AI-chip ecosystem

The approach fits China’s wider push to build an integrated domestic technology stack spanning semiconductor design and fabrication, memory, advanced packaging, AI frameworks and system integration. The logic is straightforward: if a restriction at any single layer can limit the entire system, reducing dependence requires progress across multiple layers at once.

That ecosystem is already gaining market share in China. IDC data reported by Reuters indicate that domestic Chinese GPU and AI-chip suppliers, led by Huawei, accounted for about 41% of China’s AI-accelerator server market in 2025, while NVIDIA remained the largest individual supplier with about 55%. Export controls and pressure to localize procurement are important forces behind the shift.

The figures show commercial momentum, not technological parity. Market share can reflect supply availability, procurement policy and geopolitical restrictions as well as performance. The harder test is whether domestic systems can provide competitive results at acceptable cost, power consumption and reliability.

A different kind of scaling race

Huawei is not escaping semiconductor physics. It is attempting to move part of the competition away from transistor dimensions and toward the speed of information movement, three-dimensional integration, packaging, software and cluster-scale coordination.

If Tau Scaling and LogicFolding work as claimed, a vertically integrated ecosystem could partially compensate for China’s disadvantage in leading-edge lithography. But the September smartphone chip—and later, larger AI systems—will have to demonstrate that advantage under independent measurement. For now, Huawei has proposed a different route through the bottleneck, not yet proven that it has removed the bottleneck.