Universal Topological Gates from Braiding and Fusing Anyons on Real Quantum Hardware

On July 15, 2026, researchers from Microsoft and Quantinuum published a landmark experiment in Nature demonstrating universal topological quantum gates by braiding and fusing non-Abelian anyons on a 54-qubit quantum processor . This is the first time anyon fusion was used as a computational primitive to achieve a universal gate set on real quantum hardware, closing a longstanding gap in topological quantum computing. The work represents a significant experimental validation of a theoretical framework that had been understood for years but never realized on actual hardware .

What gap does it close?

Earlier work, including Quantinuum's own 2023–2024 demonstrations on H2, showed that non-Abelian anyons could be created and braided. However, braiding alone does not supply a computationally universal gate set for the simplest non-Abelian topological orders . The S₃ topological order used in this experiment is a "minimally non-Abelian" generalization of the toric code. Braiding alone leaves it non-universal, but the team proved that treating anyon fusion as an additional computational primitive supplies the missing gates . This closes a theoretical gap that had been known for decades: simple non-Abelian anyon models could support fault-tolerant quantum computation in principle, but no one had shown how to realize a complete universal gate set on a real processor until now .

Prior theoretical work on universal gates via fusion and measurement operations on SU(2)₄ anyons had shown that augmenting braiding with fusion could yield universal gate sets , but this experiment on the S₃ quantum double is the first full hardware implementation.

How was it demonstrated on Quantinuum's H2 trapped-ion processor?

The experiment was performed on Quantinuum's System Model H2, a trapped-ion processor with 54 fully connected qubits, high-fidelity gates, and mid-circuit measurement and feedback . The team prepared the ground-state wavefunction of S₃ topological order on a kagome lattice, creating non-Abelian anyons as excitations . They then executed circuits that braided anyons around each other (topological exchange operations) and fused anyons together—bringing them to the same location to measure their combined charge . The fusion outcomes were used as part of the logical gate operation, enabling a universal gate set that braiding alone could not produce . The results were verified by comparing measured anyon fusion probabilities against theoretical predictions for S₃ anyon models .

The H2 processor's architecture was critical: its racetrack-shaped ion trap provides all-to-all connectivity, which allowed the team to create the topological state with the necessary complexity while maintaining high fidelity . Earlier demonstrations on H2 with 27 qubits had already shown non-Abelian topological order and anyon braiding with per-site fidelity exceeding 98.4% , but the 54-qubit scale was necessary to support the fusion-based universal gate set.

Key limitations and remaining challenges

Despite the breakthrough, the experiment has several important limitations that the researchers themselves acknowledge:

• Not yet fault-tolerant in practice: The anyon operations were implemented on physical qubits using error-mitigation techniques; the experiment does not yet achieve the intrinsic topological protection that would make gates fault-tolerant at scale .
• Scalability: The demonstration required 54 qubits and deep adaptive circuits. Scaling to useful problem sizes will demand many more qubits, lower error rates, and better error correction tailored to topological codes .
• Fusion vs. fault tolerance: Fusion inherently destroys anyons, so it must be used carefully to preserve the topological encoding. The paper acknowledges that fusion-based gates compromise fault tolerance unless combined with active error correction . A subsequent theoretical work on the S₃ quantum double proposes a specialized anyon interferometer to remotely measure total charge and avoid fusion altogether, which could help address this limitation .
• Limited to S₃ anyons: S₃ is the smallest non-Abelian group that supports universal computation via braiding and fusion. Future work aims to realize richer anyon models (e.g., Fibonacci anyons) that are theoretically more powerful but harder to engineer . Recent work has demonstrated Fibonacci anyon braiding with 94% charge measurement accuracy and 98% golden ratio fidelity , showing that alternative approaches are also advancing.
• Next steps: The authors propose integrating these topological gates with active quantum error correction codes, scaling to larger topological orders, and eventually demonstrating a logical qubit with an error rate below the physical qubit floor .

Broader context and significance

Topological quantum computation offers a fundamentally different vision from conventional qubit-based approaches: instead of fighting errors with ever-more-complex error correction, it encodes information in the braiding patterns of quasiparticles in a way that is naturally protected from local noise . The demonstration that a minimal non-Abelian topological order can support a universal gate set when fusion is added as a primitive shows that useful topological computation may be achievable with simpler physical systems than previously required. As the S₃ topological order is the simplest non-Abelian group that can be prepared with finite-depth adaptive circuits , this result opens a practical path toward scalable topological quantum processors.