AMD Fires Back at NVIDIA: 256-Core EPYC Venice Projected to Beat Vera by 3.3x in Rack-Scale AI

The battle for the soul of the AI data center has shifted from GPUs to the humble CPU. On June 10, 2026, AMD published a technical blog and methodology paper that directly challenges the performance narrative NVIDIA has built around its new Vera CPU. The core of AMD's argument is not that Vera is a slow chip, but that NVIDIA is measuring the wrong thing. For the coming wave of agentic AI, where thousands of AI agents require constant CPU-side orchestration, database access, web serving, and caching, AMD insists the only meaningful benchmark is total rack-scale throughput under a fixed power budget .

Instead of a direct single-core drag race, AMD proposes a thought experiment: give each platform a 100 kW rack power budget and see how much real-world agentic work it can handle. In that scenario, AMD's internal modeling suggests its high-core-count EPYC processors dramatically outperform NVIDIA's Vera, not because each core is vastly faster, but because superior power efficiency allows many more cores to be packed into the same power envelope .

The Rack-Scale Scorecard: How AMD Says the CPUs Stack Up

AMD's modeled comparison normalizes all platforms to a 100 kW dual-socket (2P) server rack. It combines six workloads central to agentic AI—SPECrate 2017 integer performance, server-side Java, NGINX web serving, Redis, Memcached, and relational databases—into a geometric mean throughput score, with Vera as the baseline .

Platform	Cores per CPU	Normalized Rack-Level Throughput (Geometric Mean)
NVIDIA Vera (88C, Olympus ARM)	88	1.00x (baseline)
Intel Xeon 6980P (128C, Granite Rapids-AP)	128	1.46x
AMD EPYC 9965 "Turin" (192C, Zen 5)	192	2.37x
AMD EPYC "Venice" (256C, Zen 6)	256	3.30x (projected)

The workload-level breakdown for the upcoming Venice chip against Vera is particularly aggressive, with projections ranging from a 2.40x gain in integer performance to a 4.05x advantage in relational database transactions (TPROC-C) .

The Methodology Debate: Cores Per Watt vs. Performance Per Core

The disagreement comes down to a fundamental physics and efficiency calculation. AMD's model estimates that its chips have a lower normalized 2P node power than Vera. When every rack is capped at 100 kW, lower power draw per node means you can physically install more servers. AMD's analysis shows that while a Vera rack has a normalized node count of 1.00x, an EPYC 9965 rack can fit 1.86x normalized cores, and a Venice rack can fit 2.08x .

Rack-level throughput is then calculated as the product of per-node performance and the number of nodes per rack. Even if Vera were slightly faster on a per-core basis—a point that early independent benchmarks have supported for some tasks —AMD's argument is that it’s mathematically impossible to overcome the sheer core-count advantage that its more power-efficient designs enable in a power-constrained rack .

AMD does, however, make claims about per-core performance itself. Its methodology paper estimates that a 64-core Venice CPU will deliver a 27% higher per-core SPECrate performance than Vera's 88-core processor, and that even a 96-core Venice chip will maintain an 11% per-core advantage .

The Two Lenses of the CPU War

This is a classic benchmark framing war, with each company choosing the measurement that best suits its design philosophy .

• NVIDIA's Lens: Single-Socket Speed. NVIDIA positions Vera as "the CPU for agents," built for massively concurrent sandbox environments where fast, single-chip performance is paramount. The company's own technical blog claims Vera delivers up to 1.5x higher agentic sandbox performance compared to competitive x86 platforms, supported by 1.2 TB/s of memory bandwidth and custom Olympus cores with NVIDIA Spatial Multithreading .
• AMD's Lens: Rack-Scale Service Density. AMD reframes the discussion around production agentic AI environments, where a GPU executes the model but the CPU handles everything around it—orchestration, user authentication, caching layers, and database queries. In this view, serving 10,000 concurrent AI agents requires massive multi-threaded throughput, which is best served by maximizing core density per rack .

Critical Caveats Behind the 3.3x Number

While AMD's headline figures are eye-catching, they require a healthy dose of context.

• All Numbers Are AMD's Internal Estimates. The most important caveat is that the Venice figures in particular are pre-silicon projections, not independently measured results. The analysis itself is a model, not a test .
• NVIDIA Tells a Different Story with Different Workloads. NVIDIA's own benchmarks, using its selection of sandbox and compilation workloads, often show Vera outperforming AMD's current high-end EPYC processors on a single-socket basis .
• Apples and Oranges Benchmarks. AMD's six-workload geometric mean focuses on CPU-side infrastructure services. It does not include the agentic sandbox compilation, code execution, and tool-call workloads that form the centerpiece of NVIDIA's Vera marketing .
• Vera's Power Is Estimated by AMD. A key driver of AMD's rack-level advantage is the assumption of Vera's node power. In AMD's normalized model, Vera has the highest 2P node power, which limits the number of nodes per rack. This is an AMD modeling assumption, not an independently verified measurement of final silicon .

Availability: When Is the Silicon Actually Coming?

The production timelines add another layer to the competitive dynamic.

• AMD EPYC 9965 "Turin" (Zen 5): This 192-core processor is the current flagship and the basis for AMD's claim of 2.37x rack throughput over Vera. It is shipping now .
• AMD EPYC "Venice" (Zen 6, 256-core): AMD confirmed on May 21, 2026, that Venice has entered volume production on TSMC's advanced 2nm process technology . The server-grade EPYC Venice series is expected to launch in the second half of 2026, with desktop Zen 6 models following later .
• NVIDIA Vera: NVIDIA began shipping the first Vera CPUs to leading AI labs such as Anthropic, OpenAI, and Oracle Cloud Infrastructure in mid-May 2026, with broader partner availability expected in the second half of the year .

As both chips approach general availability, the debate will finally move from vendor slide decks to third-party data center testing. Until then, the most useful conclusion may not be about which CPU is faster, but about ensuring your infrastructure evaluation aligns with the specific workload you intend to run.