TSMC’s CoWoS Bottleneck Is Rewiring the AI-Chip Supply Chain

That makes the package a hard production gate. A logic die can be fabricated and still fail to become a usable accelerator if the HBM and advanced packaging slot are unavailable. One Epoch AI analysis estimated that NVIDIA, Google, AMD, and Amazon together accounted for more than 90% of global CoWoS packaging and HBM supply by value in 2025, while representing about 12% of advanced-logic-die production. The asymmetry shows why logic-die capacity alone is a poor measure of finished AI-chip supply.

Reported CoWoS lead times of roughly 52–78 weeks and bookings extending into 2027 give the bottleneck a multiyear character. The practical consequence is allocation: customers able to reserve capacity early are better positioned than smaller or later entrants, even when their compute dies are ready.

TSMC is expanding quickly, but demand is expanding too

Industry estimates put TSMC’s CoWoS capacity at roughly 35,000 wafer starts per month in late 2024, rising toward approximately 120,000–130,000 per month by the end of 2026. That is a substantial increase, but reports still describe the market as constrained because new capacity is being absorbed by AI demand.

The estimates vary by definition and coverage. Some refer to TSMC-only CoWoS, while others include CoWoS-like capacity or outsourced packaging. Morgan Stanley, for example, forecast global CoWoS demand of 2.694 million wafers in 2027, up from 1.394 million in 2026, while expecting TSMC’s monthly capacity to reach 200,000 wafers by the end of 2027. These are forecasts rather than confirmed production figures, but they illustrate the scale of the investment required merely to keep pace.

TSMC is also exploring longer-term alternatives. A reported CoPoS panel-packaging pilot uses 310×310 mm panels, with mass production targeted for late 2028 or 2029. That timeline makes it a potential future scaling path, not an immediate answer to the current shortage.

Why Intel Malaysia is suddenly relevant

Reports citing industry sources say some backend advanced-packaging orders for shared major customers are spilling over to Intel’s Malaysia operations because TSMC’s CoWoS capacity is full. If accurate, the arrangement would blur a traditional competitive boundary: TSMC could keep its front-end wafer flow moving while Intel performs selected backend stages.

The claim has not been publicly confirmed by TSMC or Intel in the supplied reporting. A separate data point offers circumstantial support: industry coverage cites approximately $1.3 billion of HBM shipments into Malaysia. That is consistent with HBM being routed to a Malaysian packaging location, but the trade data does not identify the customer, product, process, or contract terms. It therefore cannot by itself prove a specific TSMC-to-Intel order transfer.

The most defensible conclusion is narrower: Malaysia is becoming more important in the advanced-packaging flow, and Intel is positioned to capture some work as customers search for capacity outside TSMC’s fully allocated system.

EMIB-T offers a second architecture—but not an instant release valve

Intel’s EMIB approach uses localized silicon bridges embedded in the package substrate rather than a single large silicon interposer spanning the package. That can reduce the amount of silicon used and may improve material economics for large multi-die designs.

Industry reports put EMIB-T package yield near 90% and packaging quotes roughly 40–50% below TSMC’s CoWoS offering. Those figures are useful indicators of commercial potential, but they are not equivalent to independently published, like-for-like yield or pricing data.

The central weakness is the substrate. Unimicron has described EMIB-T as not yet mature, with Unimicron, Ibiden, and Shinko Electric reportedly targeting an initial substrate yield of about 50% for mass production at the end of 2027. A package-level yield near 90% is therefore not enough: the entire system also needs a reliable supply of large, complex ABF substrates with acceptable yield.

Intel has described EMIB-T as moving toward high-volume production for customer ramps in 2027. That makes it a credible diversification option, but mostly a medium-term one. It is unlikely to remove the industry-wide CoWoS constraint immediately.

CoWoS versus EMIB-T: what the public evidence shows

Package-size comparisons require caution. The usable maximum depends on the CoWoS generation, reticle and interposer design, bridge placement, substrate, HBM count, thermal limits, and power requirements. Publicly cited maximum dimensions or reticle counts from different roadmaps should not be treated as a simple apples-to-apples ranking.

The near-term distinction is clearer than the size comparison: CoWoS is available now but rationed, while EMIB-T is intended to add a qualified alternative from 2027 onward.

Unimicron and ASE become strategic parts of the answer

The bottleneck is creating opportunities beyond the two headline rivals. Unimicron is working with Intel and Japanese suppliers on EMIB-T substrates while expanding ABF-substrate capacity for AI GPUs, custom AI silicon, and high-performance computing. Its challenge is not merely installing more capacity; it is raising yield on unusually large and complex substrates.

ASE, as an outsourced semiconductor assembly and test provider, can absorb assembly and testing work and benefit from overflow demand. But ASE is not automatically a drop-in replacement for TSMC’s integrated CoWoS flow. Transfers still depend on customer qualification, interposer or RDL sourcing, HBM integration, and test requirements.

This is why the industry response is becoming more distributed. Capacity is being sought across foundries, OSATs, substrate makers, memory suppliers, and materials vendors rather than at a single packaging line.

What the shortage means for AI infrastructure

The immediate effect is slower and less predictable accelerator delivery. A shortage of either HBM or advanced packaging can delay complete systems, even when the underlying logic dies are available. It also favors the largest customers with the purchasing power and planning horizon to reserve scarce capacity in advance.

For data-center operators, that can delay the installation of training clusters and increase the value of long-term supply commitments. For chip designers, it raises the cost of choosing a package architecture: switching away from CoWoS is not simply a matter of finding an open assembly line. The design must be requalified around a different interconnect structure, substrate, HBM configuration, thermal solution, and test flow.

The shortage also reaches into adjacent semiconductor inputs. Reporting describes pressure on HBM, ABF substrates, assembly and test, packaging materials, and related components. However, the available evidence does not establish a quantified shortage or price shock across particular non-AI industries. The strongest supported claim is a crowding-out effect within the semiconductor backend and memory ecosystems, not a measured economy-wide disruption.

The bottom line

TSMC’s CoWoS constraint is changing the competitive map of AI hardware. It is pushing selected backend work toward Intel Malaysia, increasing the strategic value of ASE and substrate suppliers, and making Intel’s EMIB-T more relevant as a second packaging route.

But the evidence supports a measured verdict rather than a takeover narrative. CoWoS remains the qualified production workhorse; EMIB-T’s reported cost and package-yield advantages are offset by unresolved ABF-substrate yield and a 2027 volume timeline. The AI-chip supply chain is diversifying because it has to—not because a complete replacement for TSMC is already operating at scale.