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Intel EMIB-T vs. TSMC CoWoS: The Emerging Second Source for AI Chip Packaging
Intel’s EMIB T is a credible second source option for large AI and HBM packages: it replaces a package wide silicon interposer with localized bridges and adds TSV based vertical power delivery. CoWoS capacity has expanded dramatically, with estimates ranging from roughly 13,000 wafer starts per month in late 2023 to...
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Key takeaways
- Intel’s EMIB T is a credible second source option for large AI and HBM packages: it replaces a package wide silicon interposer with localized bridges and adds TSV based vertical power delivery.
- CoWoS capacity has expanded dramatically, with estimates ranging from roughly 13,000 wafer starts per month in late 2023 to 120,000–140,000 in 2026, but industry estimates still expected a supply gap of about 10% by y...
- MediaTek is the clearest reported adopter of a dual CoWoS/EMIB T approach; reports also point to evaluations or interest from Google, Meta, Broadcom, Nvidia, SK hynix and Amazon, with varying—and often unconfirmed—lev...
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openai.comCreate a landscape editorial hero image for this Studio Global article: How is Intel positioning its EMIB-T advanced packaging technology as an alternative to TSMC’s capacity-constrained CoWoS platform for large. Article summary: Intel is positioning EMIB‑T as a second-source packaging option for very large AI accelerators: one that can attach logic and HBM without consuming a package-wide silicon interposer or scarce CoWoS capacity. It is a cred. Topic tags: general, general web, user generated. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, watermarks, charts with fak
Large AI accelerators are no longer limited only by leading-edge logic manufacturing. The package that joins compute dies to high-bandwidth memory (HBM) has become a strategic constraint. Intel is pitching EMIB-T as an alternative route: a modular package architecture that uses silicon only at the high-density connections and adds a more direct power-delivery path for HBM-heavy designs. 18
The important distinction is commercial as much as technical. EMIB-T offers designers another packaging path when CoWoS allocations are tight, but it has not yet been publicly validated as a wholesale replacement for TSMC’s established ecosystem.
The core architectural difference
CoWoS: a broad interconnect layer beneath the package
In the classic CoWoS-S approach, compute dies and HBM stacks sit on a large silicon interposer. That interposer provides a dense wiring plane across much of the package, enabling the very wide connections required by advanced accelerators. 4
This is a proven architecture for large HBM systems, but a package-wide interposer increases the amount of silicon required and ties capacity to a specialized advanced-packaging supply chain.
CoWoS is not a single, static design. TSMC’s CoWoS-L uses a redistribution-layer (RDL) interposer with localized silicon interconnect bridges, rather than relying on one monolithic silicon interposer. That means the practical comparison is not simply “interposer versus no interposer.” 7
EMIB: silicon bridges only where they are needed
Intel’s Embedded Multi-die Interconnect Bridge (EMIB) places small silicon bridges inside an organic package substrate. The bridges provide dense, short connections between adjacent dies—such as logic and HBM—while lower-density routing is handled by the substrate. 18
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The design goal is to avoid putting a large silicon interposer beneath the entire package. Intel says locally embedded bridges can provide a more cost-effective option for logic-to-logic and logic-to-HBM integration because the bridge type can be selected for the specific interconnect required. 18
EMIB-T: EMIB with vertical power delivery
EMIB-T adds through-silicon vias (TSVs) to the embedded bridge. Intel says the addition responds to HBM-driven demand for vertical power delivery with minimal DC and AC noise. 18
Put simply, standard EMIB primarily supplies high-density lateral connections between neighboring dies. EMIB-T introduces a more direct vertical route through the bridge for power delivery, addressing the electrical demands of larger, higher-current packages. Reporting also describes it as a way to reduce voltage droop relative to the earlier power path. 18
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Why Intel sees an opening
The opening is capacity concentration. CoWoS output has grown rapidly: industry estimates place TSMC capacity at roughly 13,000 wafer starts per month in late 2023 and around 120,000–130,000 by late 2026. 44 Yet demand has expanded alongside capacity, and institutional-investor estimates reported by TrendForce projected the supply-demand gap would narrow from about 20% in mid-2026 to about 10% by year-end—not disappear.
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Nvidia is estimated to hold about 60% of CoWoS allocation, although that figure is not a TSMC disclosure. If accurate, it underscores why custom-chip developers and hyperscalers may value a qualified second supplier even as total CoWoS capacity rises. 30
For Intel, EMIB-T is therefore not merely an emergency overflow option. It is a pitch for long-term supply-chain optionality: designers can qualify another package architecture for future accelerator generations, potentially reducing exposure to a single packaging route and a tightly allocated capacity pool.
Who is using or evaluating EMIB-T?
Public evidence varies sharply by company. The following categories are more useful than treating every report as a confirmed production win.
| Company or program | Publicly reported status | What can be concluded |
|---|---|---|
| MediaTek | MediaTek reportedly said it would use CoWoS and EMIB-T in parallel for a very large custom AI ASIC. |
This is the strongest reported sign of adoption, but it is a parallel strategy—not evidence that EMIB-T replaces CoWoS. |
| Google TPU | Reporting based on unnamed sources says Google has evaluated Intel packaging with MediaTek for a future TPU, and a separate report said Google booked Intel packaging for more than 3 million TPUs in 2028. |
A potentially significant program, but Google has not publicly confirmed the program details or volume. |
| Broadcom and Meta | Both have been reported to be considering a move or partial shift toward EMIB, with Meta’s inference silicon discussed as a possible target. |
Treat this as evaluation or interest, not a disclosed production award. |
| Nvidia | Reports describe Nvidia as interested in alternatives, but available reporting does not establish a public, committed EMIB-T volume program. |
Interest and partnership activity should not be conflated with EMIB-T adoption. |
| SK hynix | SK hynix has reportedly been testing Intel EMIB for HBM integration. |
Testing matters for ecosystem qualification, but it is not a production commitment. |
| Amazon Trainium | Some reporting describes discussions or interest around Amazon’s Trainium line. |
There is insufficient public evidence of a finalized EMIB-T award for Trainium 4. |
This distinction matters because advanced packaging must be qualified across electrical performance, thermals, mechanical reliability, substrate supply, HBM interoperability and sustained manufacturing yield. A customer evaluation is an early ecosystem signal—not proof of high-volume deployment.
What a 2027 Intel ramp would mean
Reports have associated EMIB-T volume expansion with the 2026–2027 period. 9
25 If Intel achieves meaningful scale in the second half of 2027, its biggest opportunity may come after the most acute CoWoS shortage begins to ease.
That timing favors multi-sourcing, not a sudden platform switch:
- CoWoS remains deeply established. Its ecosystem, process maturity and customer experience make it a strong default for many leading AI designs.
- EMIB-T offers a distinct engineering and supply-chain option. Localized bridges can reduce dependence on a package-wide silicon interposer, while TSVs target the power-delivery demands of large HBM packages.
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- A smaller shortage still has strategic value. Even if the estimated gap falls to 10%, allocation risk and launch timing remain consequential for multi-year accelerator roadmaps.
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The bottom line
Intel’s most plausible near-term win is not to unseat CoWoS across the AI market. It is to become a durable second advanced-packaging supplier for selected HBM-heavy accelerators and hyperscaler ASICs.
EMIB-T’s appeal rests on a specific proposition: use localized embedded bridges instead of a package-wide silicon interposer, then add TSV-enabled vertical power delivery for the electrical demands of next-generation packages. 18 Whether that proposition becomes a major commercial business will depend less on reported customer interest than on demonstrated yields, HBM qualification, reliability and repeatable high-volume execution.
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Intel’s EMIB T is a credible second source option for large AI and HBM packages: it replaces a package wide silicon interposer with localized bridges and adds TSV based vertical power delivery.
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Intel’s EMIB T is a credible second source option for large AI and HBM packages: it replaces a package wide silicon interposer with localized bridges and adds TSV based vertical power delivery. CoWoS capacity has expanded dramatically, with estimates ranging from roughly 13,000 wafer starts per month in late 2023 to 120,000–140,000 in 2026, but industry estimates still expected a supply gap of about 10% by y...
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MediaTek is the clearest reported adopter of a dual CoWoS/EMIB T approach; reports also point to evaluations or interest from Google, Meta, Broadcom, Nvidia, SK hynix and Amazon, with varying—and often unconfirmed—lev...