The AI-chip supply bottleneck is increasingly moving beyond leading-edge wafers and HBM memory to advanced packaging. TSMC’s CoWoS remains the established platform for combining processors, chiplets, and high-bandwidth memory, but its capacity is heavily committed. Intel is using that pressure to position EMIB-T as a second path for large AI accelerators—especially custom ASICs and designs where package size, cost, or supply diversification matter more than maximum interconnect density.

The strategic message is important: Intel is not presenting EMIB-T as a universal, drop-in replacement for CoWoS. It is offering a different packaging architecture that could complement CoWoS across the AI-chip market.

EMIB-T and CoWoS use different packaging approaches

TSMC’s CoWoS family generally places a broad, high-density interconnect layer beneath the logic dies and HBM. CoWoS-S uses a full silicon interposer, while CoWoS-L combines a redistribution-layer interposer with localized silicon bridges. That architecture has made CoWoS a leading option for high-bandwidth GPU and HBM packages. 3336

Intel’s EMIB instead embeds small silicon bridges in an organic package substrate only where adjacent dies require dense connections. EMIB-T adds through-silicon vias, or TSVs, to the bridge. The change is intended to improve vertical power and signal delivery in complex heterogeneous packages without requiring a full-package silicon interposer. 53435

That distinction gives each platform a different potential advantage:

• CoWoS: a broad, dense routing fabric that suits designs requiring maximum bandwidth density and close integration between logic and HBM.
• EMIB-T: localized bridges that use less silicon interposer area and can be arranged around multiple chiplets and memory stacks.
• Trade-off: EMIB-T shifts more responsibility to the package substrate, while CoWoS has a longer-established position in high-volume AI and HBM designs. 3641

Intel’s pitch: large packages without a full interposer

Intel has reported EMIB-T configurations larger than 120 × 120 millimeters, with more than nine reticle-equivalents of silicon, up to 12 HBM modules, four dense compute chiplets, and more than 20 bridges. Those specifications put the technology in the range of very large AI accelerator and HBM-heavy designs. 1132

However, package size alone does not establish a decisive advantage. CoWoS-L is reported to support packages around 5.5 times reticle size today, while TSMC has described a roadmap extending beyond 14 times reticle size later in the decade. EMIB-T’s stronger argument is therefore modularity and potential manufacturing economics—not an uncontested lead in every measure of package scale. 33

Industry reports have attributed potential cost savings of up to 50% to EMIB-T and have cited package yields approaching 90%. Those figures should be treated cautiously: they are reported estimates rather than independently disclosed, like-for-like production results, and substrate yield is still described as a key hurdle. 1631

Which companies are adopting or evaluating EMIB-T?

The public evidence separates one confirmed supporter from a larger group of reported prospects.

MediaTek: public support for both platforms

MediaTek has publicly said that it supports both TSMC’s CoWoS and Intel’s EMIB, allowing customers to choose between the approaches. Reuters reported that the company views both technologies as part of its custom-silicon offering. 17

Separate industry reporting says MediaTek plans to use CoWoS and EMIB-T in parallel for large AI ASIC programs. The clearest conclusion is that MediaTek has publicly confirmed dual-platform support; the exact production allocation for individual customer programs is less certain. 18

Broadcom and Meta: reported evaluation

Broadcom and Meta have been reported as evaluating EMIB or a partial shift away from CoWoS, with cost and supply diversification cited as motivations. The available reporting does not establish a publicly disclosed, high-volume EMIB-T production award for either company. 1824

Google: strong reported interest, but no disclosed contract in the reviewed evidence

Several reports link Google’s future TPU programs to Intel packaging, including claims that Google has selected or ordered Intel packaging for a future generation. Other coverage describes the move as expected adoption rather than a confirmed public contract. Because Intel and Google have not disclosed definitive production terms in the evidence reviewed here, Google should be classified as a strong reported prospect—not a confirmed EMIB-T customer. 192123

Nvidia: interest, but no disclosed EMIB-T award

Nvidia has been linked to interest in EMIB-T as CoWoS capacity remains tight. There is no disclosed high-volume EMIB-T award in the cited evidence. Nvidia remains the largest reported consumer of TSMC’s CoWoS capacity, which gives it a reason to investigate additional packaging options even if its highest-end products continue using CoWoS. 1842

Amazon: reported targeting of EMIB-T

Amazon’s AWS Trainium 3 has been reported as a prospective EMIB-T user. That claim has not been publicly confirmed by Amazon or Intel in the sources reviewed, so it is best treated as a reported target rather than an announced production program. 21

SK hynix: reported HBM integration work

SK hynix has reportedly been testing Intel EMIB-based 2.5D packaging with its own HBM and reviewing materials and suppliers for possible future production. This indicates technology evaluation or collaboration; it does not by itself demonstrate a firm commitment to purchase high-volume Intel packaging services. 25

The status overview is therefore:

• Publicly confirmed support: MediaTek supports both CoWoS and EMIB.
• Reported evaluation or interest: Broadcom, Meta, Nvidia, and SK hynix.
• Reported prospective adoption: Google and Amazon.
• Publicly disclosed high-volume EMIB-T awards: not established in the reviewed evidence.

Why CoWoS capacity is creating an opening

Analyst estimates show why chip designers are seeking alternatives. KGI estimates TSMC’s annual CoWoS capacity at approximately 670,000 wafers in 2025 and 1 million in 2026, with Nvidia taking about 65% of 2026 capacity. 42

Other forecasts are substantially more aggressive, projecting approximately 1.275 million wafers in 2026 and 2.31 million in 2027. Demand estimates also vary: a Morgan Stanley-based forecast cited in industry reporting puts key-customer demand at roughly 1.384 million wafers in 2026 and 2.682 million in 2027. Differences in definitions, ramp timing, and the mix of CoWoS variants make these figures forecasts rather than settled market totals. 1648

Even with TSMC expanding capacity, the estimates point to continued pressure. One report says global CoWoS demand could approach 1 million wafers in 2026, while Nvidia alone could account for roughly 60% of total demand. Other estimates put Nvidia’s share of TSMC capacity at roughly 50% or more through 2027. These figures are analyst or industry estimates, not TSMC disclosures, and the percentages differ depending on whether the comparison is against total demand, TSMC capacity, or a specific CoWoS variant. 264243

The broader concentration is also significant. One estimate says Nvidia, Google, AMD, and Amazon together consumed more than 90% of CoWoS packaging capacity in 2025. If accurate, that concentration leaves other chip designers exposed to allocation decisions and gives customers an incentive to qualify another advanced-packaging supplier. 44

Why customers want a second packaging route

The diversification case rests on four practical considerations.

Capacity and scheduling risk

A chip can have sufficient compute wafers and HBM but still be delayed if the packaging slot is unavailable. Reports describe CoWoS capacity as heavily booked through 2026, making advanced packaging a production constraint rather than a final assembly detail. 4546

Cost potential

A localized-bridge design can reduce the amount of silicon used compared with a full interposer. That creates the possibility of lower package cost, although the benefit depends on substrate complexity, yield, assembly processes, and the specific design. Reported 50% savings should therefore be viewed as a target or industry estimate, not a guaranteed customer result. 631

Fit for custom AI ASICs

Hyperscalers and other chip designers increasingly build custom accelerators with different combinations of compute chiplets, I/O, and HBM. EMIB-T’s bridge-based approach may be attractive when a package needs a large footprint and multiple localized high-density connections, particularly for custom ASICs and inference-oriented designs. CoWoS may remain preferable where the design demands the highest uniform routing density and mature HBM integration. 3637

Supplier diversification

Qualifying Intel gives chip designers another advanced-packaging ecosystem and reduces reliance on a single platform for future capacity planning. That does not mean customers will abandon TSMC: a dual-sourcing strategy can preserve CoWoS for some products while directing other designs to EMIB-T.

Intel’s revenue timeline

Intel expects advanced-packaging revenue, including EMIB-T, to begin ramping in the second half of 2027, become a meaningful run-rate contributor in 2028, and reach fuller scale in 2029. 34

Intel CFO Dave Zinsner has described potential advanced-packaging agreements worth billions of dollars per year per customer, but customer names, volumes, and signed-contract economics have not been fully disclosed. The opportunity is therefore substantial but execution-dependent: Intel must convert reported interest into qualified designs, achieve reliable substrate and package yields, and scale production on schedule. 83

The likely outcome: coexistence before replacement

EMIB-T’s near-term role is most plausibly that of a complementary platform. CoWoS has the installed base and high-volume experience for leading AI and HBM packages. EMIB-T offers a different route for customers that need additional capacity, very large heterogeneous packages, potentially lower cost, or leverage in supplier negotiations.

The decisive test will not be whether Intel can demonstrate a large package in engineering material. It will be whether customers move from evaluation to repeatable, high-volume production by the time Intel’s revenue ramp begins in 2027. Until then, EMIB-T is a credible alternative and an important competitive pressure on CoWoS—but not yet a proven wholesale replacement.

The AI-chip supply bottleneck is increasingly moving beyond leading-edge wafers and HBM memory to advanced packaging. TSMC’s CoWoS remains the established platform for combining processors, chiplets, and high-bandwidth memory, but its capacity is heavily committed. Intel is using that pressure to position EMIB-T as a second path for large AI accelerators—especially custom ASICs and designs where package size, cost, or supply diversification matter more than maximum interconnect density.

The strategic message is important: Intel is not presenting EMIB-T as a universal, drop-in replacement for CoWoS. It is offering a different packaging architecture that could complement CoWoS across the AI-chip market.

EMIB-T and CoWoS use different packaging approaches

TSMC’s CoWoS family generally places a broad, high-density interconnect layer beneath the logic dies and HBM. CoWoS-S uses a full silicon interposer, while CoWoS-L combines a redistribution-layer interposer with localized silicon bridges. That architecture has made CoWoS a leading option for high-bandwidth GPU and HBM packages. 3336

Intel’s EMIB instead embeds small silicon bridges in an organic package substrate only where adjacent dies require dense connections. EMIB-T adds through-silicon vias, or TSVs, to the bridge. The change is intended to improve vertical power and signal delivery in complex heterogeneous packages without requiring a full-package silicon interposer. 53435

That distinction gives each platform a different potential advantage:

• CoWoS: a broad, dense routing fabric that suits designs requiring maximum bandwidth density and close integration between logic and HBM.
• EMIB-T: localized bridges that use less silicon interposer area and can be arranged around multiple chiplets and memory stacks.
• Trade-off: EMIB-T shifts more responsibility to the package substrate, while CoWoS has a longer-established position in high-volume AI and HBM designs. 3641

Intel’s pitch: large packages without a full interposer

Intel has reported EMIB-T configurations larger than 120 × 120 millimeters, with more than nine reticle-equivalents of silicon, up to 12 HBM modules, four dense compute chiplets, and more than 20 bridges. Those specifications put the technology in the range of very large AI accelerator and HBM-heavy designs. 1132

However, package size alone does not establish a decisive advantage. CoWoS-L is reported to support packages around 5.5 times reticle size today, while TSMC has described a roadmap extending beyond 14 times reticle size later in the decade. EMIB-T’s stronger argument is therefore modularity and potential manufacturing economics—not an uncontested lead in every measure of package scale. 33

Industry reports have attributed potential cost savings of up to 50% to EMIB-T and have cited package yields approaching 90%. Those figures should be treated cautiously: they are reported estimates rather than independently disclosed, like-for-like production results, and substrate yield is still described as a key hurdle. 1631

Which companies are adopting or evaluating EMIB-T?

The public evidence separates one confirmed supporter from a larger group of reported prospects.

MediaTek: public support for both platforms

MediaTek has publicly said that it supports both TSMC’s CoWoS and Intel’s EMIB, allowing customers to choose between the approaches. Reuters reported that the company views both technologies as part of its custom-silicon offering. 17

Separate industry reporting says MediaTek plans to use CoWoS and EMIB-T in parallel for large AI ASIC programs. The clearest conclusion is that MediaTek has publicly confirmed dual-platform support; the exact production allocation for individual customer programs is less certain. 18

Broadcom and Meta: reported evaluation

Broadcom and Meta have been reported as evaluating EMIB or a partial shift away from CoWoS, with cost and supply diversification cited as motivations. The available reporting does not establish a publicly disclosed, high-volume EMIB-T production award for either company. 1824

Google: strong reported interest, but no disclosed contract in the reviewed evidence

Several reports link Google’s future TPU programs to Intel packaging, including claims that Google has selected or ordered Intel packaging for a future generation. Other coverage describes the move as expected adoption rather than a confirmed public contract. Because Intel and Google have not disclosed definitive production terms in the evidence reviewed here, Google should be classified as a strong reported prospect—not a confirmed EMIB-T customer. 192123

Nvidia: interest, but no disclosed EMIB-T award

Nvidia has been linked to interest in EMIB-T as CoWoS capacity remains tight. There is no disclosed high-volume EMIB-T award in the cited evidence. Nvidia remains the largest reported consumer of TSMC’s CoWoS capacity, which gives it a reason to investigate additional packaging options even if its highest-end products continue using CoWoS. 1842

Amazon: reported targeting of EMIB-T

Amazon’s AWS Trainium 3 has been reported as a prospective EMIB-T user. That claim has not been publicly confirmed by Amazon or Intel in the sources reviewed, so it is best treated as a reported target rather than an announced production program. 21

SK hynix: reported HBM integration work

SK hynix has reportedly been testing Intel EMIB-based 2.5D packaging with its own HBM and reviewing materials and suppliers for possible future production. This indicates technology evaluation or collaboration; it does not by itself demonstrate a firm commitment to purchase high-volume Intel packaging services. 25

The status overview is therefore:

• Publicly confirmed support: MediaTek supports both CoWoS and EMIB.
• Reported evaluation or interest: Broadcom, Meta, Nvidia, and SK hynix.
• Reported prospective adoption: Google and Amazon.
• Publicly disclosed high-volume EMIB-T awards: not established in the reviewed evidence.

Why CoWoS capacity is creating an opening

Analyst estimates show why chip designers are seeking alternatives. KGI estimates TSMC’s annual CoWoS capacity at approximately 670,000 wafers in 2025 and 1 million in 2026, with Nvidia taking about 65% of 2026 capacity. 42

Other forecasts are substantially more aggressive, projecting approximately 1.275 million wafers in 2026 and 2.31 million in 2027. Demand estimates also vary: a Morgan Stanley-based forecast cited in industry reporting puts key-customer demand at roughly 1.384 million wafers in 2026 and 2.682 million in 2027. Differences in definitions, ramp timing, and the mix of CoWoS variants make these figures forecasts rather than settled market totals. 1648

Even with TSMC expanding capacity, the estimates point to continued pressure. One report says global CoWoS demand could approach 1 million wafers in 2026, while Nvidia alone could account for roughly 60% of total demand. Other estimates put Nvidia’s share of TSMC capacity at roughly 50% or more through 2027. These figures are analyst or industry estimates, not TSMC disclosures, and the percentages differ depending on whether the comparison is against total demand, TSMC capacity, or a specific CoWoS variant. 264243

The broader concentration is also significant. One estimate says Nvidia, Google, AMD, and Amazon together consumed more than 90% of CoWoS packaging capacity in 2025. If accurate, that concentration leaves other chip designers exposed to allocation decisions and gives customers an incentive to qualify another advanced-packaging supplier. 44

Why customers want a second packaging route

The diversification case rests on four practical considerations.

Capacity and scheduling risk

A chip can have sufficient compute wafers and HBM but still be delayed if the packaging slot is unavailable. Reports describe CoWoS capacity as heavily booked through 2026, making advanced packaging a production constraint rather than a final assembly detail. 4546

Cost potential

A localized-bridge design can reduce the amount of silicon used compared with a full interposer. That creates the possibility of lower package cost, although the benefit depends on substrate complexity, yield, assembly processes, and the specific design. Reported 50% savings should therefore be viewed as a target or industry estimate, not a guaranteed customer result. 631

Fit for custom AI ASICs

Hyperscalers and other chip designers increasingly build custom accelerators with different combinations of compute chiplets, I/O, and HBM. EMIB-T’s bridge-based approach may be attractive when a package needs a large footprint and multiple localized high-density connections, particularly for custom ASICs and inference-oriented designs. CoWoS may remain preferable where the design demands the highest uniform routing density and mature HBM integration. 3637

Supplier diversification

Qualifying Intel gives chip designers another advanced-packaging ecosystem and reduces reliance on a single platform for future capacity planning. That does not mean customers will abandon TSMC: a dual-sourcing strategy can preserve CoWoS for some products while directing other designs to EMIB-T.

Intel’s revenue timeline

Intel expects advanced-packaging revenue, including EMIB-T, to begin ramping in the second half of 2027, become a meaningful run-rate contributor in 2028, and reach fuller scale in 2029. 34

Intel CFO Dave Zinsner has described potential advanced-packaging agreements worth billions of dollars per year per customer, but customer names, volumes, and signed-contract economics have not been fully disclosed. The opportunity is therefore substantial but execution-dependent: Intel must convert reported interest into qualified designs, achieve reliable substrate and package yields, and scale production on schedule. 83

The likely outcome: coexistence before replacement

EMIB-T’s near-term role is most plausibly that of a complementary platform. CoWoS has the installed base and high-volume experience for leading AI and HBM packages. EMIB-T offers a different route for customers that need additional capacity, very large heterogeneous packages, potentially lower cost, or leverage in supplier negotiations.

The decisive test will not be whether Intel can demonstrate a large package in engineering material. It will be whether customers move from evaluation to repeatable, high-volume production by the time Intel’s revenue ramp begins in 2027. Until then, EMIB-T is a credible alternative and an important competitive pressure on CoWoS—but not yet a proven wholesale replacement.