How ASML’s High‑NA EUV Is Changing Chip Manufacturing

This higher resolution matters because advanced chip manufacturing increasingly depends on printing extremely fine transistor and interconnect structures. With conventional EUV, manufacturers often rely on complex multi‑patterning techniques to achieve the required dimensions. High‑NA systems can print smaller patterns in fewer exposures, simplifying the process.

Industry estimates suggest High‑NA tools can pattern features around roughly 8 nm in a single pass, compared with roughly 13 nm for today’s EUV scanners. Actual usable dimensions still depend on process design, photoresists, masks, and chip architecture.

The practical result: fewer lithography steps on critical layers, potentially reducing overlay errors and manufacturing complexity.

When the First High‑NA Chips Will Arrive

ASML and Intel announced plans to bring High‑NA EUV into manufacturing during the mid‑2020s, with Intel placing the first order for the TWINSCAN EXE:5200 system.

Early systems began shipping in the 2025–2026 timeframe, initially for testing, process development, and early production ramps.

However, the timeline for widespread chip production is longer. Industry forecasts suggest:

• Early risk production or limited manufacturing: 2025–2026
• Broader high‑volume production across the industry: around 2027–2028

This gap is typical in semiconductor manufacturing. Installing a lithography system does not immediately translate to full production; fabs must develop process recipes, integrate the tool with other equipment, and validate yields.

Technical and Cost Advantages Over Previous EUV

High‑NA EUV offers several key benefits compared with earlier EUV generations.

Higher resolution
The jump from 0.33 NA to 0.55 NA significantly improves the optical resolution of the scanner, allowing smaller patterns to be printed with fewer exposures.

Fewer patterning steps
Reducing multi‑patterning lowers process complexity, which can shorten production cycles and reduce sources of manufacturing error.

Potential yield improvements
Simpler patterning can reduce alignment and overlay challenges, which are major sources of yield loss in advanced nodes.

Economic trade‑offs
Each High‑NA EUV machine is extremely expensive—around $350 million per system—so chipmakers must balance the capital cost against the savings from fewer process steps, reduced masks, and higher chip density.

Which Companies Are Deploying High‑NA Systems

The earliest adopters are the companies pushing the most advanced manufacturing nodes.

Intel
Intel is widely considered the first major adopter. It ordered the first High‑NA EUV production system from ASML as part of a long‑term collaboration to bring the technology into manufacturing.

Samsung
Samsung has reportedly ordered multiple High‑NA systems, with deliveries expected starting in 2025 and continuing into 2026, following earlier research deployments.

SK hynix
The memory manufacturer has also installed High‑NA systems in development facilities to support future DRAM processes.

TSMC
TSMC appears more cautious about near‑term large‑scale adoption, reportedly delaying broader deployment while evaluating costs and process benefits.

When Mass Production Is Expected

Industry forecasts converge around a two‑phase rollout:

• Mid‑2020s: early manufacturing and technology development
• Late‑2020s (around 2027–2028): broader high‑volume manufacturing using High‑NA EUV at nodes around the 1.4‑nm class

This period coincides with the semiconductor industry’s transition into what some analysts call the “angstrom era,” where process nodes are measured in fractions of a nanometer.

Why AI Is Driving Demand for These Machines

ASML’s growth outlook is closely tied to the rapid expansion of AI computing. The company says the semiconductor market is shifting from “chips everywhere” to “AI chips everywhere,” with AI workloads driving demand across many segments of the industry.

The company has also reported stronger orders and a rising revenue outlook as chipmakers accelerate capacity expansion plans in response to AI demand.

Because every leading‑edge chip—especially GPUs and AI accelerators—requires advanced lithography, ASML’s tools effectively sit at the bottleneck of the most advanced semiconductor production.

Where India Fits Into the Picture

India is building its domestic semiconductor ecosystem under the India Semiconductor Mission, with government officials saying the country aims to begin commercial chip production in 2026.

However, these initial fabs are focused on establishing foundational manufacturing capacity. High‑NA EUV is designed for the world’s most advanced nodes, so near‑term deployments are concentrated in established semiconductor hubs such as the United States, South Korea, and Taiwan.

Over time, as India’s semiconductor industry expands, it could create demand for equipment support, services, and eventually more advanced lithography infrastructure.

The Bottom Line

High‑NA EUV is the semiconductor industry’s next major manufacturing milestone. By boosting optical resolution and reducing patterning complexity, it enables the continued scaling of transistors into the angstrom era.

The first chips made with these machines should appear in limited production around 2025–2026, but the real impact will likely arrive later in the decade when multiple chipmakers begin high‑volume manufacturing with High‑NA systems.

For companies racing to build the most powerful AI chips, access to these $350‑million lithography tools may become one of the most decisive advantages in the global semiconductor industry.