ASML High‑NA EUV: The Technology Powering Sub‑2nm Chips

That improvement matters because modern chips often require extremely fine patterns that are difficult to print in one step. Before High‑NA, chipmakers frequently used multi‑patterning, where a single layer is printed several times and stitched together. This increases complexity, manufacturing time, and defect risk. High‑NA EUV can reduce the need for those extra exposures by printing smaller features directly.

In practice, that means:

• Smaller transistor features and tighter interconnects
• Simpler manufacturing flows for some critical layers
• Potential improvements in yield and production cycle time

The technology is widely seen as a key enabler for sub‑2 nm logic nodes and next‑generation memory scaling.

The machines themselves: cost and capability

High‑NA EUV tools are among the most complex machines ever built for manufacturing.

• Typical price: about $350 million to $400 million per system.
• Physical scale: comparable to a double‑decker bus with thousands of components.
• Throughput: roughly 175–200 wafers per hour for current production systems, with earlier models around 185 wafers per hour and future versions targeting higher speeds.

Because each tool costs so much, chipmakers must weigh whether the benefits—fewer lithography steps and higher density—justify the capital expense.

Which companies are installing High‑NA systems

Early adoption has been limited to the largest semiconductor manufacturers.

• Intel was among the first to receive High‑NA systems and has collaborated closely with ASML on development.
• Samsung Electronics has reportedly taken deliveries intended for future production lines.
• SK hynix has installed a High‑NA machine to accelerate development of next‑generation memory.

Industry reports also suggest that companies including Intel, Samsung, and SK hynix are expected to be among the earliest adopters as the technology moves toward full production deployment.

When the first chips and mass production are expected

High‑NA EUV has already moved beyond prototype status.

• Initial machines began shipping to customers in 2025, with broader deployment beginning in 2026.
• Industry forecasts suggest large‑scale mass production using High‑NA EUV could begin around 2027–2028.

In the near term, both generations of EUV tools will coexist. Standard EUV systems continue improving throughput and precision, and they will still be used for many layers even at advanced nodes.

Why High‑NA matters for logic and memory chips

The benefits differ slightly between chip categories.

Logic processors

For CPUs, GPUs, and AI accelerators, High‑NA enables:

• Smaller gate and interconnect features
• Higher transistor density
• Potential performance and power‑efficiency improvements

These capabilities are particularly important for AI accelerators and high‑performance computing chips, where transistor density directly affects compute capability.

Memory chips

High‑NA also supports scaling for memory technologies such as advanced DRAM, which must keep shrinking feature sizes to maintain capacity growth. Some forecasts suggest the technology could help enable sub‑2 nm DRAM structures required for future AI‑focused memory systems.

The role of AI demand in ASML’s strategy

ASML’s business is tightly linked to the semiconductor industry’s need for more powerful chips. In recent financial disclosures, the company reported €32.7 billion in total net sales and €9.6 billion in net income in 2025, with demand increasingly driven by artificial intelligence workloads.

Executives say the rapid growth of AI computing—particularly the need for higher compute density and high‑bandwidth memory—is strengthening long‑term demand for advanced lithography systems.

High‑NA EUV therefore represents both a technological and commercial milestone: it extends Moore’s Law scaling while reinforcing ASML’s position as the only supplier of EUV lithography systems used for cutting‑edge chips.

ASML’s global expansion and India partnership

Alongside technology development, ASML is expanding partnerships in emerging semiconductor ecosystems.

In 2026, Tata Electronics and ASML signed an agreement to support India’s first front‑end semiconductor fabrication facility in Gujarat, part of the country’s push to build a domestic chip industry.

The project involves an estimated $11 billion investment in a 300 mm wafer fab and is one of several semiconductor initiatives underway in India.

While the facility will use ASML lithography equipment, publicly available information does not confirm that it will deploy High‑NA EUV specifically.

The bigger picture

High‑NA EUV is the most significant upgrade to semiconductor lithography since the introduction of EUV itself. By enabling finer patterns in fewer steps, it gives chipmakers a path to continue scaling transistor density into the sub‑2 nm era.

But the technology also comes with enormous cost and engineering complexity. Only a handful of companies can afford the tools, and it may take several years before High‑NA becomes a standard part of mainstream manufacturing.

If current timelines hold, the late‑2020s will likely mark the moment when High‑NA EUV moves from cutting‑edge experimentation to the foundation of the world’s most advanced chips.