Inside Huawei's Plan to Bypass EUV Lithography and Match 1.4nm Chips by 2031

What is the Tau (τ) Scaling Law?

The Tau Scaling Law is a proposed replacement for Moore's Law, which has historically been defined by packing more, smaller transistors onto a flat piece of silicon. Tau (τ) shifts the goal from minimizing the physical space between transistors to minimizing the time it takes for a signal to travel across a chip .

By optimizing for signal transit time rather than pitch scaling, the Tau framework aims to improve functional density and performance-per-watt on a system-wide level, incorporating the transistor, interconnect, packaging, and system design all at once . The core idea is that modern chip bottlenecks are often about data movement, not just transistor count, and that this metric can be attacked with architectural innovation rather than finer photolithography .

LogicFolding: The 3D Architecture Bypassing EUV

LogicFolding is the concrete silicon architecture built on the Tau scaling principles. Instead of laying out a chip's logic circuits on a single planar layer, the architecture "folds" them into two or three vertically stacked layers . This approach has two key effects:

1. It shortens wiring paths. By moving circuits into the third dimension, the physical distance electrical signals must travel is drastically reduced. This lowers resistive-capacitive (RC) loads and boosts overall speed and power efficiency .
2. It packs in more transistors without smaller nodes. Huawei claims the stacking method boosts transistor density by approximately 55% and improves power efficiency without requiring the sub-atomic precision of EUV tools .

Crucially, these density gains do not depend on advanced lithography. The chips are fabricated on mature 7nm-class process nodes at China's SMIC, using existing deep ultraviolet (DUV) lithography systems that are not blocked by current U.S. export controls . The company states it has already mass-produced 381 chip models over six years using the foundational co-optimization techniques that LogicFolding extends .

The Roadmap: From a 2026 Kirin Chip to a 2031 1.4nm Equivalent

Huawei presented a concrete, two-step roadmap:

• Late 2026: The first commercial LogicFolding chip will ship in a Kirin system-on-a-chip (SoC), likely for the Mate 90 series, using a dual-layer design. This chip is projected to achieve a transistor density of 238 MTr/mm², a figure that brings it roughly on par with TSMC's 3nm-class node performance . Early performance claims include a peak clock speed of 3.1GHz and a 40% improvement in power-core efficiency .
• By 2031: Huawei plans to introduce a three-layer LogicFolding design that reaches transistor density equivalent to a 1.4nm-class process, a target TSMC itself aims to reach by 2028 .

Jensen Huang's Response: A Contradictory Threat Assessment

Nvidia CEO Jensen Huang responded to Huawei's unveiling with a two-part message that evolved over subsequent days.

Just before the ISCAS conference, Huang had already acknowledged Huawei's dominance in an important market segment. He told CNBC that U.S. export restrictions had made it impossible for Nvidia to compete, stating that the company has "largely ceded" the Chinese AI chip market to Huawei .

On the direct question of whether LogicFolding posed a threat to TSMC's foundry leadership, his public stance sharpened and then softened. Initial reports suggested Huang found Huawei's ability to achieve competitive AI performance on mature 7nm nodes to be a "serious threat" to the business model that depends on customers always needing the very latest node .

However, days later on May 29, 2026, Huang delivered a more dismissive verdict to reporters in Taipei. "This is a breakthrough for Huawei, but it's not a threat for TSMC," he said. "TSMC has been using die stacking and 3D packaging for how long now? Almost 10 years. And so TSMC's technology is very advanced." .

Reality Check: The Caveats Behind the Hype

For all its strategic boldness, Huawei's vision comes with significant asterisks that are crucial for a balanced view.

• Huawei's claims are unverified. The stated 55% transistor density boost is an internal figure that has not been independently confirmed by third-party chip analysis firms . The company is describing a "1.4nm-equivalent" density achieved through architecture, not a lithographic 1.4nm node.
• Thermal and yield challenges are real. Stacking logic layers generates significantly more heat in a smaller volume, and ensuring defect-free manufacturing across multiple stacked layers is notoriously difficult. Industry analysts caution that these factors could limit the commercial viability and performance of large-scale 3D-logic chips .
• The "equivalent density" is nuanced. Huawei is not claiming it will etch transistors at a 1.4nm scale. Instead, it aims to pack a functionally equivalent number of transistors into a given area by building upwards, a distinction that matters for power, heat, and cost comparisons with monolithic chips on advanced nodes .

In essence, Huawei has proposed a post-Moore's Law playbook that reframes the semiconductor race around smart 3D design rather than pure lithographic supremacy. While the 2026 Kirin chip will be an early litmus test, the ultimate 2031 goal remains a long-term bet that hinges on solving the extreme physics of 3D logic stacking.