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Why SK hynix Is Testing Intel EMIB for HBM, and What Intel Must Prove Next
As of May 2026, SK hynix was reportedly testing its HBM with Intel’s EMIB 2.5D packaging and reviewing production materials—but no signed high volume contract or formal production award has been publicly confirmed. The appeal is supply chain diversification: EMIB uses localized silicon bridges instead of a package w...
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Key takeaways
- As of May 2026, SK hynix was reportedly testing its HBM with Intel’s EMIB 2.5D packaging and reviewing production materials—but no signed high volume contract or formal production award has been publicly confirmed.
- The appeal is supply chain diversification: EMIB uses localized silicon bridges instead of a package wide interposer, potentially reducing cost, thickness, defect exposure and dependence on TSMC’s CoWoS capacity.
- Intel’s reported approximately 90% EMIB T yield is encouraging, but substrate yield was separately reported near 50%, leaving qualification, volume capacity and end to end reliability as the decisive tests.
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openai.comCreate a landscape editorial hero image for this Studio Global article: How did Intel Foundry secure SK Hynix as a formal customer for its EMIB advanced packaging technology to integrate SK Hynix’s high-bandwidth. Article summary: The evidence supports an early, supply-chain-driven EMIB collaboration with SK hynix—not a publicly confirmed formal production-customer win. In May 2026, SK hynix was reportedly testing integration of its HBM with Intel. Topic tags: general, general web, user generated, news. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, watermarks, charts w
Intel did not publicly demonstrate that it had secured SK hynix as a formal, high-volume EMIB customer. The evidence points to an earlier stage: in May 2026, SK hynix was reportedly conducting research and integration tests using its HBM with Intel’s EMIB-based 2.5D packaging while evaluating materials and components for possible production. Neither company had confirmed a commercial agreement in the reporting available at the time. 4
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That distinction matters. A packaging test can validate whether HBM, logic dies, substrates and assembly processes work together. It does not prove that a customer has committed production volumes, selected a final supplier or accepted Intel’s economics and reliability targets.
The reported path from testing to production preparation
The collaboration appears to have developed in three linked steps:
- Integration testing: SK hynix reportedly tested the combination of its HBM and system semiconductors on Intel EMIB substrates. The immediate objective was to assess whether EMIB could provide another route for connecting memory and logic dies.
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- Materials and component evaluation: Reports said SK hynix was reviewing the materials and components needed for potential mass production. That suggests an industrialization study rather than a completed production decision.
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- Supplier qualification: LG Innotek reportedly supplied early EMIB-related FC-BGA substrate samples to SK hynix while seeking a place in the supply chain. The samples were described as an early engineering stage, and commercial adoption remained uncertain.
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This progression is strategically meaningful because advanced packaging is not just a technology problem. Intel and SK hynix would also need a qualified substrate ecosystem, repeatable assembly processes, sufficient capacity and performance data from complete HBM packages.
Why SK hynix would evaluate an alternative to CoWoS
The reported motivation is diversification. TSMC’s CoWoS packaging has become central to AI accelerators, but industry reporting has described advanced-packaging capacity as constrained. A second packaging route could give a memory supplier and its customers more flexibility when allocating AI-chip production. 4
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Intel’s EMIB takes a different architectural approach from traditional full-interposer CoWoS designs. Instead of placing a large silicon interposer beneath the package, EMIB embeds smaller silicon bridges inside an organic package substrate. The bridges are positioned only where neighboring dies need very dense connections, while lower-density signals can use conventional substrate wiring. 8
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That design can offer several potential advantages:
- Less package-wide silicon: Smaller bridge dies can reduce dependence on a large interposer and limit the amount of silicon exposed to defects.
- Potential cost and scale benefits: A localized-bridge design may use less interposer material and can support large, modular packages without requiring one silicon layer to span the entire footprint.
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- Lower mechanical and thermal complexity in some designs: Avoiding a package-wide silicon interposer may reduce thickness, warpage and thermal-mechanical stress, although the actual result depends on the complete package.
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- Supply-chain optionality: Customers could use EMIB as an alternative or second source when CoWoS capacity is unavailable or too concentrated.
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The stakes are high for HBM-based AI packages. If a large interposer or a late-stage assembly step fails after an expensive logic die and multiple HBM stacks have been combined, the resulting scrap exposure can be substantial. Analysts have identified cost, thickness, yield risk, capacity constraints and scrap as weaknesses associated with interposer-based HBM packaging. 23
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What the reported 90% yield does—and does not—prove
Reports in August said Intel’s EMIB-T packaging yield had reached approximately 90%, with mass production targeted for 2027. The same reporting placed substrate yield near 50%, making the substrate a major remaining bottleneck. 1
Those figures should be read carefully. The 90% number is a reported supply-chain figure, not a broadly audited guarantee for every EMIB-T product or for a complete package containing HBM and logic. More importantly, a high bridge or package-process yield does not automatically produce a high final yield. Substrates, bonding, thermal behavior, electrical testing, reliability qualification and customer-specific assembly all affect the result.
Intel therefore has to prove an end-to-end manufacturing proposition:
- EMIB-T must meet the customer’s bandwidth, power-delivery and thermal requirements.
- Substrate suppliers must achieve consistent yields at production volumes.
- Intel must deliver capacity on the schedule customers need.
- The complete package must pass reliability and qualification testing.
- Yield and cycle time must make the alternative economically attractive after all assembly costs are included.
Seok-Hee Lee strengthens the relationship—but is not evidence of a contract
Intel appointed Seok-Hee Lee, a former chief executive of SK hynix and SK On, as an executive vice president overseeing advanced packaging, system integration and back-end technology development and manufacturing at Intel Foundry. 2
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The appointment could improve Intel’s industry relationships and execution as it tries to scale EMIB-T and related packaging technologies. It also gives Intel leadership with direct experience in the memory industry. But the hiring does not establish that SK hynix signed an EMIB production agreement. It is better understood as part of Intel’s broader effort to professionalize and expand its packaging business.
EMIB is an alternative to CoWoS, not an automatic replacement
CoWoS retains important advantages. It is mature, widely integrated into AI-chip supply chains and designed for extremely dense die-to-HBM connections. TSMC’s CoWoS-L was reported to be in mass production at package sizes up to 5.5 times reticle area, demonstrating that the incumbent platform is continuing to scale. 18
EMIB may be more attractive for package architectures that benefit from localized connections, modularity and a potentially smaller silicon footprint. But it can introduce its own challenges in routing, substrate design, assembly, thermal management and qualification. The right comparison is not simply “small bridges versus large interposer”; it is the total performance, cost, yield and time-to-volume of the finished package.
That is why the SK hynix work matters even without a confirmed order. HBM suppliers are close to the technical and commercial requirements of AI-chip packaging. Successful testing could help Intel validate its platform with an important ecosystem participant. It still would not show that EMIB has displaced CoWoS across the market.
What this means for Intel Foundry’s packaging ambitions
Intel is positioning advanced packaging as a standalone foundry service rather than only an internal capability for Intel-designed processors. Industry reports have described management expectations for packaging revenue to exceed $1 billion and potentially grow into multibillion-dollar annual deals, while other reports said customers were considering capacity commitments or prepayments. 41
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A credible SK hynix validation would support that strategy in two ways. First, it would show that Intel’s packaging can work with an external memory supplier’s HBM. Second, it could help Intel attract custom AI-chip designers that want an alternative to TSMC’s packaging ecosystem.
MediaTek publicly said customers could choose between TSMC and Intel advanced-packaging technologies. That is a meaningful ecosystem signal, but it is not the same as a disclosed large EMIB production order. 33
Reports have also linked EMIB-T to possible Google TPU activity, but the evidence provided here is not strong enough to treat reported Google volumes or revenue as confirmed bookings. The same caution applies to claims about other major GPU customers: evaluation, design-in and early-production discussions should not be presented as durable production commitments. 3
The remaining constraints
Intel’s opportunity is real but narrow. TSMC remains the default partner for many leading AI accelerators because its packaging technology, qualification history, customer integrations and production footprint are already established. There is also insufficient reliable public evidence that Nvidia or AMD has committed to significant EMIB diversification.
The next milestones are therefore more important than the headline of a reported collaboration:
- confirmation that SK hynix’s testing advances beyond research and engineering samples;
- qualification of substrates and materials, including whether LG Innotek can move beyond early samples;
- stable end-to-end yields rather than an isolated process-yield figure;
- production capacity that arrives when customers need it; and
- a disclosed external product entering volume production.
The best-supported conclusion is cautious but significant: SK hynix’s EMIB work is an encouraging validation signal driven partly by the need for more HBM-packaging options. It is not yet proof that Intel secured a formal production customer, replaced CoWoS or locked in durable multibillion-dollar packaging revenue.
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What is the short answer to "Why SK hynix Is Testing Intel EMIB for HBM, and What Intel Must Prove Next"?
As of May 2026, SK hynix was reportedly testing its HBM with Intel’s EMIB 2.5D packaging and reviewing production materials—but no signed high volume contract or formal production award has been publicly confirmed.
What are the key points to validate first?
As of May 2026, SK hynix was reportedly testing its HBM with Intel’s EMIB 2.5D packaging and reviewing production materials—but no signed high volume contract or formal production award has been publicly confirmed. The appeal is supply chain diversification: EMIB uses localized silicon bridges instead of a package wide interposer, potentially reducing cost, thickness, defect exposure and dependence on TSMC’s CoWoS capacity.
What should I do next in practice?
Intel’s reported approximately 90% EMIB T yield is encouraging, but substrate yield was separately reported near 50%, leaving qualification, volume capacity and end to end reliability as the decisive tests.
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