Inside Intel Panther Lake’s 18A Compute Tile

Hardware & Co’s photos offer a look at Intel processor wafers without requiring a chip to be cut out and prepared for a conventional close-up die photograph. The Panther Lake images show the broad arrangement of the processor’s tiles; read alongside technical analysis, they help explain how Intel separates CPU work from graphics and divides CPU cores by power role. 184

How the wafer photos were made

Around Computex 2026, Hardware & Co encountered Intel Core and Xeon processor wafers and photographed them with a camera. The site described the close-up photography as challenging because of the density of the circuitry. These are images of intact wafers, rather than destructive teardown images made by removing and preparing individual dies. 18

The site reported photographing Panther Lake silicon—including two Panther Lake variations—and Intel’s Xeon 6900P family, also known as Clearwater Forest. 18 The photos were published in July and drew wider international notice after the enthusiast InstLatX64 highlighted them. 3

What Panther Lake’s 18A compute tile contains

Panther Lake is Intel’s Core Ultra Series 3 processor family. Its CPU cores sit on a compute tile built using Intel 18A. The tile combines different core types rather than treating every CPU core as interchangeable. 7

The layout includes Cougar Cove performance cores, Darkmont efficiency cores, and a separate low-power cluster of Darkmont cores. In the described maximum configuration, the compute tile can include up to four Cougar Cove cores, up to eight Darkmont E-cores, and up to four low-power Darkmont E-cores. Actual configurations can vary. 27

The compute tile also contains media and display engines. Xe3 graphics, by contrast, sit on a separate graphics tile; they are not part of the 18A compute tile. The graphics tile’s manufacturing process can vary by version. 41

Why the low-power cluster matters—and what the photo can’t prove

The separate low-power cluster gives the processor a lower-power CPU domain for suitable workloads. In principle, lighter tasks can run there rather than requiring the higher-performance cores to handle them. Dedicated media and display engines also provide hardware for those functions. Together, these design choices explain how the processor can assign work to different parts of the chip according to the task. 47

That is a design rationale, not a battery-life result. A wafer photo can show where major blocks sit, but it does not measure how long a laptop runs on a charge or establish the effect of the layout under real-world use.

The key takeaway

Hardware & Co’s camera captured intact wafers; the value of the Panther Lake images is the view they offer of the chip’s overall organization. The 18A compute tile brings together performance and efficiency cores, a distinct low-power core cluster, and media and display engines, while Xe3 graphics live on a separate tile. The layout points to workload-specific power management, but battery-life claims require measurements beyond a photograph. 1847