Why Google may want a direct TSMC line for TPUs — without dropping MediaTek

So the safer reading is conditional: if Google moves some wafer or CoWoS capacity coordination closer to TSMC, that would be a shift in purchasing power, packaging control and schedule visibility. It would not, by itself, prove that MediaTek has lost every technical or engineering role in the project.

The reported split of work matters

TPU, short for Tensor Processing Unit, is Google’s custom AI accelerator and falls into the ASIC category of chips built for specific workloads. Reports describe Google as keeping the most strategic design work in-house.

TechNews reported that, in Google’s cooperation with MediaTek, Google is responsible for the Compute Die design and procurement of high-bandwidth memory, or HBM. MediaTek is reported to handle the I/O Die design, all wafer procurement and back-end packaging integration.

Inside, summarising reporting from The Information, also said the next TPU is still mostly designed by Google, while MediaTek mainly provides the communications input/output design between the TPU and related components, assists with production quality control, and serves as the party placing orders with TSMC.

That distinction is crucial. MediaTek is not described as merely a broker sitting between Google and TSMC. But it is also not described as the full architect of Google’s TPU. Its reported role sits in the I/O, manufacturing coordination, quality and packaging-integration layers. A more direct Google-TSMC link could therefore reduce MediaTek’s control over procurement and scheduling without eliminating its I/O or engineering contribution.

Why TSMC’s CoWoS capacity is the centre of gravity

For advanced AI chips, design is only half the battle. The other half is getting enough manufacturing and advanced packaging capacity to ship at scale. That is where TSMC’s CoWoS packaging becomes strategically important.

Next Apple, citing foreign media, reported that Google’s dual-supplier approach allows it to seek TSMC CoWoS advanced packaging allocation through both MediaTek and Broadcom, helping accelerate TPU v7e mass production. Business Weekly also reported that MediaTek had added TSMC advanced process and CoWoS packaging capacity for Google’s v7e and v8e projects, and that TSMC’s 2027 CoWoS capacity for MediaTek’s Google project was rumoured to increase more than sevenfold.

The timeline adds pressure. Business Weekly reported that moving from wafer production to completed CoWoS packaging and testing takes about eight to nine months. It also reported that, if later certification proceeds smoothly, output from the TPU v7e risk production run could be treated as production supply. When the bottleneck is packaging slots and production timing, it is easy to see why Google would want a clearer, more direct view of the TSMC pipeline.

Four reasons Google may want a more direct TSMC relationship

1. Securing scarce CoWoS capacity

Multiple reports connect Google’s TPU ramp with TSMC’s CoWoS capacity. If demand for TPU v7e and v8e rises quickly, direct visibility into wafer starts, packaging queues and test schedules could reduce uncertainty. For a hyperscale cloud company, the ability to know when chips will be ready can matter as much as the chip design itself.

2. Improving cost control — though direct does not automatically mean cheaper

Inside reported that Google planned to work with MediaTek on a lower-cost TPU, partly because MediaTek’s quote was lower than Broadcom’s. That suggests Google was already looking for a more cost-efficient TPU supply model.

Still, public information does not prove that direct TSMC ordering would necessarily be cheaper than the current structure. The real cost would depend on contracts, capacity commitments, packaging configuration and who carries integration risk. The better conclusion is that a closer TSMC relationship could give Google more control over cost drivers, not that it guarantees a lower bill.

3. Shortening the decision chain

In the reported MediaTek arrangement, MediaTek handles wafer procurement and back-end packaging integration. It is also described as helping with quality control and placing orders with TSMC. That means MediaTek is not only providing design-related services; it is also managing part of the manufacturing coordination chain.

If Google wants faster decisions on wafer starts, CoWoS allocation, testing and certification, a more direct role with TSMC would be a logical supply-chain adjustment. That kind of change could separate two functions that are currently linked: who supports I/O and engineering, and who controls production capacity and delivery timing.

4. Reducing dependence on any one ASIC partner

Google’s move to involve MediaTek has already been interpreted as part of a dual-supplier strategy. Next Apple reported that Google had previously relied heavily on Broadcom across TPU-related architecture, IP, I/O services and system integration, and that seeking a second source was a way to reduce exposure to cost, supply and technology-timing risks from relying too heavily on one partner.

Inside also reported that even if Google turns more toward MediaTek, its relationship with Broadcom may continue, meaning Broadcom and MediaTek could split Google TPU orders. A stronger direct relationship with TSMC would fit the same logic: Google would keep more control over the scarce manufacturing layer instead of letting any one design-service or integration partner become the single gatekeeper.

What this means for MediaTek

The current evidence points more to role redistribution than immediate exclusion. TechNews reported that MediaTek has entered the design of Google’s eighth-generation TPU, or TPUv8x, with revenue contribution expected to begin in the fourth quarter of 2026. The same report said market interpretation linked later project revenue, expected from 2028, to a possible advanced eighth-generation TPU, or TPUv8e.

TechNews also reported that one reason MediaTek won Google business from Broadcom was its SerDes IP, a high-speed communications technology used to move data efficiently between chip components. That is closely aligned with the I/O-focused role described in other reports.

So even if Google takes back more direct control over wafer purchasing, CoWoS allocation or delivery schedules, MediaTek could still remain relevant in areas such as I/O Die design, SerDes, quality control and system-level engineering support.

Three signals to watch next

First, watch CoWoS allocation. Business Weekly reported that TSMC’s 2027 CoWoS capacity for MediaTek’s Google project was rumoured to rise more than sevenfold. If that figure changes, it would directly affect the expected TPU ramp.

Second, watch the TPU v7e risk-production schedule. Business Weekly reported that MediaTek’s first Google TPU, v7e, was expected to enter risk production at the end of the first quarter of 2026. Whether that output can be treated as production supply depends on the certification process.

Third, watch whether MediaTek’s role shifts from wafer procurement and packaging integration toward I/O, SerDes, quality and engineering support. TechNews and Inside both describe MediaTek as having I/O and manufacturing-coordination responsibilities, not as having fully exited Google’s TPU programme.

Bottom line

If Google seeks a more direct path to TSMC for future TPUs, the most likely reason is control: control of CoWoS capacity, production timing, cost structure and supply-chain visibility. That is different from proving that MediaTek has been pushed out.

Based on current reporting, Google appears to be making its TPU supply chain more direct and more diversified. MediaTek’s risk is not necessarily an immediate loss of all Google TPU work. The bigger question is whether its role in wafer procurement, packaging and scheduling becomes narrower while its I/O and engineering-support role remains in place.